Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1063582 [patent_doc_number] => 06849868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Methods and apparatus for resistance variable material cells' [patent_app_type] => utility [patent_app_number] => 10/100450 [patent_app_country] => US [patent_app_date] => 2002-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5337 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849868.pdf [firstpage_image] =>[orig_patent_app_number] => 10100450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100450
Methods and apparatus for resistance variable material cells Mar 13, 2002 Issued
Array ( [id] => 6727723 [patent_doc_number] => 20030183913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Method of eliminating back-end rerouting in ball grid array packaging' [patent_app_type] => new [patent_app_number] => 10/098840 [patent_app_country] => US [patent_app_date] => 2002-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20030183913.pdf [firstpage_image] =>[orig_patent_app_number] => 10098840 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/098840
Method of eliminating back-end rerouting in ball grid array packaging Mar 13, 2002 Issued
Array ( [id] => 1281453 [patent_doc_number] => 06646342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Semiconductor chip and multi-chip module' [patent_app_type] => B2 [patent_app_number] => 10/097140 [patent_app_country] => US [patent_app_date] => 2002-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 11506 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646342.pdf [firstpage_image] =>[orig_patent_app_number] => 10097140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097140
Semiconductor chip and multi-chip module Mar 13, 2002 Issued
Array ( [id] => 1299417 [patent_doc_number] => 06623992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'System and method for determining a subthreshold leakage test limit of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 10/094549 [patent_app_country] => US [patent_app_date] => 2002-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 5655 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/623/06623992.pdf [firstpage_image] =>[orig_patent_app_number] => 10094549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094549
System and method for determining a subthreshold leakage test limit of an integrated circuit Mar 7, 2002 Issued
Array ( [id] => 1180506 [patent_doc_number] => 06744137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Bumped die and wire bonded board-on-chip package' [patent_app_type] => B2 [patent_app_number] => 10/092276 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4512 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744137.pdf [firstpage_image] =>[orig_patent_app_number] => 10092276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092276
Bumped die and wire bonded board-on-chip package Mar 4, 2002 Issued
Array ( [id] => 1107344 [patent_doc_number] => 06812909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Active semiconductor backplanes' [patent_app_type] => B1 [patent_app_number] => 10/085140 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7047 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812909.pdf [firstpage_image] =>[orig_patent_app_number] => 10085140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085140
Active semiconductor backplanes Feb 28, 2002 Issued
10/069740 Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same Feb 25, 2002 Abandoned
Array ( [id] => 1248288 [patent_doc_number] => 06673720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method for improving the reliability of flash memories' [patent_app_type] => B2 [patent_app_number] => 09/683850 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2484 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673720.pdf [firstpage_image] =>[orig_patent_app_number] => 09683850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683850
Method for improving the reliability of flash memories Feb 21, 2002 Issued
Array ( [id] => 1372141 [patent_doc_number] => 06562720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Apparatus and method for surface finishing a silicon film' [patent_app_type] => B2 [patent_app_number] => 10/077439 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562720.pdf [firstpage_image] =>[orig_patent_app_number] => 10077439 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077439
Apparatus and method for surface finishing a silicon film Feb 13, 2002 Issued
Array ( [id] => 1140796 [patent_doc_number] => 06781170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Integrated circuit base transistor structure and associated programmable cell library' [patent_app_type] => B2 [patent_app_number] => 10/082050 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4278 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781170.pdf [firstpage_image] =>[orig_patent_app_number] => 10082050 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082050
Integrated circuit base transistor structure and associated programmable cell library Feb 13, 2002 Issued
Array ( [id] => 6300530 [patent_doc_number] => 20020093070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Device and a method for thermal sensing' [patent_app_type] => new [patent_app_number] => 10/076750 [patent_app_country] => US [patent_app_date] => 2002-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7064 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093070.pdf [firstpage_image] =>[orig_patent_app_number] => 10076750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076750
Device and a method for thermal sensing Feb 11, 2002 Issued
Array ( [id] => 6415150 [patent_doc_number] => 20020125525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Nonvolatile semiconductor memory cell and method for fabricating the memory cell' [patent_app_type] => new [patent_app_number] => 10/054440 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4669 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125525.pdf [firstpage_image] =>[orig_patent_app_number] => 10054440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054440
Nonvolatile semiconductor memory cell and method for fabricating the memory cell Jan 21, 2002 Issued
Array ( [id] => 1053817 [patent_doc_number] => 06858935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Simulating euclidean wiring directions using manhattan and diagonal directional wires' [patent_app_type] => utility [patent_app_number] => 10/043808 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 9390 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/858/06858935.pdf [firstpage_image] =>[orig_patent_app_number] => 10043808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043808
Simulating euclidean wiring directions using manhattan and diagonal directional wires Jan 10, 2002 Issued
Array ( [id] => 7301216 [patent_doc_number] => 20040113193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Integrated circuit and method for making the same' [patent_app_type] => new [patent_app_number] => 10/466145 [patent_app_country] => US [patent_app_date] => 2003-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4332 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113193.pdf [firstpage_image] =>[orig_patent_app_number] => 10466145 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/466145
Integrated circuit and fabrication process Jan 8, 2002 Issued
Array ( [id] => 1155680 [patent_doc_number] => 06764917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'SOI device with different silicon thicknesses' [patent_app_type] => B1 [patent_app_number] => 10/023350 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3549 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764917.pdf [firstpage_image] =>[orig_patent_app_number] => 10023350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023350
SOI device with different silicon thicknesses Dec 19, 2001 Issued
Array ( [id] => 5814906 [patent_doc_number] => 20020039840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Semiconductor device having a multilayered interconnection structure' [patent_app_type] => new [patent_app_number] => 09/998236 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4654 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20020039840.pdf [firstpage_image] =>[orig_patent_app_number] => 09998236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998236
Method of fabricating a semiconductor device having a multilayered interconnection structure Dec 2, 2001 Issued
Array ( [id] => 6593663 [patent_doc_number] => 20020063263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Metal oxide semiconductor transistor with self-aligned channel implant' [patent_app_type] => new [patent_app_number] => 09/998615 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5998 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063263.pdf [firstpage_image] =>[orig_patent_app_number] => 09998615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998615
Metal oxide semiconductor transistor with self-aligned channel implant Nov 29, 2001 Abandoned
Array ( [id] => 7629415 [patent_doc_number] => 06818941 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Thin film electron emitter, display device using the same and applied machine' [patent_app_type] => B1 [patent_app_number] => 09/979740 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 40 [patent_no_of_words] => 8024 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818941.pdf [firstpage_image] =>[orig_patent_app_number] => 09979740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/979740
Thin film electron emitter, display device using the same and applied machine Nov 27, 2001 Issued
Array ( [id] => 1299590 [patent_doc_number] => 06624031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure' [patent_app_type] => B2 [patent_app_number] => 09/989850 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 9571 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624031.pdf [firstpage_image] =>[orig_patent_app_number] => 09989850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989850
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure Nov 19, 2001 Issued
Array ( [id] => 6593723 [patent_doc_number] => 20020063266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Semiconductor element and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/045350 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4260 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063266.pdf [firstpage_image] =>[orig_patent_app_number] => 10045350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045350
Semiconductor element and manufacturing method thereof Nov 8, 2001 Issued
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