Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17630853 [patent_doc_number] => 20220165868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => Isolation Structures of Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/666241 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666241
Isolation structures of semiconductor devices Feb 6, 2022 Issued
Array ( [id] => 19502067 [patent_doc_number] => 20240341085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/575998 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18575998 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/575998
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR Feb 6, 2022 Pending
Array ( [id] => 18147295 [patent_doc_number] => 20230021152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/665652 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665652
Semiconductor device and method for manufacturing the same Feb 6, 2022 Issued
Array ( [id] => 19399813 [patent_doc_number] => 12074201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor substrate, semiconductor device, and manufacturing methods of the same [patent_app_type] => utility [patent_app_number] => 17/588558 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 77 [patent_no_of_words] => 32429 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588558
Semiconductor substrate, semiconductor device, and manufacturing methods of the same Jan 30, 2022 Issued
Array ( [id] => 19399813 [patent_doc_number] => 12074201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor substrate, semiconductor device, and manufacturing methods of the same [patent_app_type] => utility [patent_app_number] => 17/588558 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 77 [patent_no_of_words] => 32429 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588558
Semiconductor substrate, semiconductor device, and manufacturing methods of the same Jan 30, 2022 Issued
Array ( [id] => 19399813 [patent_doc_number] => 12074201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor substrate, semiconductor device, and manufacturing methods of the same [patent_app_type] => utility [patent_app_number] => 17/588558 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 77 [patent_no_of_words] => 32429 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588558
Semiconductor substrate, semiconductor device, and manufacturing methods of the same Jan 30, 2022 Issued
Array ( [id] => 19399813 [patent_doc_number] => 12074201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor substrate, semiconductor device, and manufacturing methods of the same [patent_app_type] => utility [patent_app_number] => 17/588558 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 77 [patent_no_of_words] => 32429 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588558
Semiconductor substrate, semiconductor device, and manufacturing methods of the same Jan 30, 2022 Issued
Array ( [id] => 18857580 [patent_doc_number] => 11855177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Field effect transistors with dual silicide contact structures [patent_app_type] => utility [patent_app_number] => 17/582292 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 13758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582292
Field effect transistors with dual silicide contact structures Jan 23, 2022 Issued
Array ( [id] => 18481286 [patent_doc_number] => 11695041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/577595 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577595
Method of manufacturing a semiconductor device Jan 17, 2022 Issued
Array ( [id] => 17583256 [patent_doc_number] => 20220140111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/574899 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574899
Method of manufacturing semiconductor device Jan 12, 2022 Issued
Array ( [id] => 19110213 [patent_doc_number] => 11963346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor structure and preparation method thereof [patent_app_type] => utility [patent_app_number] => 17/647869 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7021 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647869
Semiconductor structure and preparation method thereof Jan 12, 2022 Issued
Array ( [id] => 18840291 [patent_doc_number] => 11848374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Bipolar junction transistors including a portion of a base layer inside a cavity in a dielectric layer [patent_app_type] => utility [patent_app_number] => 17/574785 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574785
Bipolar junction transistors including a portion of a base layer inside a cavity in a dielectric layer Jan 12, 2022 Issued
Array ( [id] => 19781532 [patent_doc_number] => 12230570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Integrated circuit with buried power rail and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/574073 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574073 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574073
Integrated circuit with buried power rail and methods of manufacturing the same Jan 11, 2022 Issued
Array ( [id] => 19031256 [patent_doc_number] => 11930631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Semiconductor memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/573597 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6358 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573597
Semiconductor memory device and method of fabricating the same Jan 10, 2022 Issued
Array ( [id] => 19063259 [patent_doc_number] => 11942513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor structure and method of fabricating the semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/571941 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 8578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571941
Semiconductor structure and method of fabricating the semiconductor structure Jan 9, 2022 Issued
Array ( [id] => 19875130 [patent_doc_number] => 12268016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Buried power rail formation for vertical field effect transistors [patent_app_type] => utility [patent_app_number] => 17/564571 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 43 [patent_no_of_words] => 11325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564571
Buried power rail formation for vertical field effect transistors Dec 28, 2021 Issued
Array ( [id] => 18456339 [patent_doc_number] => 20230197621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => LIQUID METAL INTERCONNECT FOR MODULAR PACKAGE SERVER ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/559365 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559365
LIQUID METAL INTERCONNECT FOR MODULAR PACKAGE SERVER ARCHITECTURE Dec 21, 2021 Issued
Array ( [id] => 18456340 [patent_doc_number] => 20230197622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => LIQUID METAL INTERCONNECT FOR MODULAR SYSTEM ON AN INTERPOSER SERVER ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/559431 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559431
Liquid metal interconnect for modular system on an interposer server architecture Dec 21, 2021 Issued
Array ( [id] => 20793043 [patent_doc_number] => 12666977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Methods, systems, apparatus, and articles of manufacture for integrated circuit package substrates with high aspect ratio through glass vias [patent_app_type] => utility [patent_app_number] => 17/558304 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 13555 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558304
Methods, systems, apparatus, and articles of manufacture for integrated circuit package substrates with high aspect ratio through glass vias Dec 20, 2021 Issued
Array ( [id] => 19627132 [patent_doc_number] => 12165981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => 3D semiconductor package with die-mounted voltage regulator [patent_app_type] => utility [patent_app_number] => 17/556346 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6804 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556346
3D semiconductor package with die-mounted voltage regulator Dec 19, 2021 Issued
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