
Dao H. Nguyen
Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2283 |
| Issued Applications | 1976 |
| Pending Applications | 142 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17900940
[patent_doc_number] => 20220310602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => GATE-ALL-AROUND DEVICES WITH ISOLATED AND NON-ISOLATED EPITAXY REGIONS FOR STRAIN ENGINEERING
[patent_app_type] => utility
[patent_app_number] => 17/213399
[patent_app_country] => US
[patent_app_date] => 2021-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6680
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213399
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/213399 | Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering | Mar 25, 2021 | Issued |
Array
(
[id] => 17339842
[patent_doc_number] => 20220006173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-06
[patent_title] => SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES
[patent_app_type] => utility
[patent_app_number] => 17/205055
[patent_app_country] => US
[patent_app_date] => 2021-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8476
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205055
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/205055 | Semiconductor packages and method of manufacturing semiconductor packages | Mar 17, 2021 | Issued |
Array
(
[id] => 18464336
[patent_doc_number] => 11688630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Shallow trench isolation filling structure in semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/202079
[patent_app_country] => US
[patent_app_date] => 2021-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 2351
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202079
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/202079 | Shallow trench isolation filling structure in semiconductor device | Mar 14, 2021 | Issued |
Array
(
[id] => 17463837
[patent_doc_number] => 20220077143
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => INTEGRATED CIRCUIT DEVICE INCLUDING METAL-OXIDE SEMICONDUCTOR TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 17/199720
[patent_app_country] => US
[patent_app_date] => 2021-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11751
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199720
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/199720 | Integrated circuit device including metal-oxide semiconductor transistors | Mar 11, 2021 | Issued |
Array
(
[id] => 18387326
[patent_doc_number] => 11658119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Backside signal interconnection
[patent_app_type] => utility
[patent_app_number] => 17/196174
[patent_app_country] => US
[patent_app_date] => 2021-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 45
[patent_no_of_words] => 12354
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196174
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/196174 | Backside signal interconnection | Mar 8, 2021 | Issued |
Array
(
[id] => 18235999
[patent_doc_number] => 11600564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Redistribution substrate, method of fabricating the same, and semiconductor package including the same
[patent_app_type] => utility
[patent_app_number] => 17/189964
[patent_app_country] => US
[patent_app_date] => 2021-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 9008
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189964
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/189964 | Redistribution substrate, method of fabricating the same, and semiconductor package including the same | Mar 1, 2021 | Issued |
Array
(
[id] => 19038254
[patent_doc_number] => 20240088069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS
[patent_app_type] => utility
[patent_app_number] => 18/260810
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15451
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18260810
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/260810 | INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS | Feb 25, 2021 | Pending |
Array
(
[id] => 19974013
[patent_doc_number] => 12342647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-24
[patent_title] => Semiconductor arrangement and method of making
[patent_app_type] => utility
[patent_app_number] => 17/181499
[patent_app_country] => US
[patent_app_date] => 2021-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5879
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181499
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/181499 | Semiconductor arrangement and method of making | Feb 21, 2021 | Issued |
Array
(
[id] => 17818672
[patent_doc_number] => 11424296
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-23
[patent_title] => Display panel and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/179773
[patent_app_country] => US
[patent_app_date] => 2021-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 11014
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179773
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/179773 | Display panel and method of manufacturing the same | Feb 18, 2021 | Issued |
Array
(
[id] => 19341495
[patent_doc_number] => 12051692
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Integrated circuit structure with front side signal lines and backside power delivery
[patent_app_type] => utility
[patent_app_number] => 17/176412
[patent_app_country] => US
[patent_app_date] => 2021-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 29
[patent_no_of_words] => 16675
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176412
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/176412 | Integrated circuit structure with front side signal lines and backside power delivery | Feb 15, 2021 | Issued |
Array
(
[id] => 17765098
[patent_doc_number] => 20220238711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => SEMICONDUCTOR DEVICE HAVING MOS TRANSISTOR FOR EFFICIENT STRESS TRANSFER
[patent_app_type] => utility
[patent_app_number] => 17/160038
[patent_app_country] => US
[patent_app_date] => 2021-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2856
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160038
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/160038 | SEMICONDUCTOR DEVICE HAVING MOS TRANSISTOR FOR EFFICIENT STRESS TRANSFER | Jan 26, 2021 | Abandoned |
Array
(
[id] => 18242869
[patent_doc_number] => 20230075180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => Semiconductor Device and Imaging Device
[patent_app_type] => utility
[patent_app_number] => 17/796916
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 36060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796916
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/796916 | Semiconductor device and imaging device | Jan 25, 2021 | Issued |
Array
(
[id] => 18371861
[patent_doc_number] => 11652043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-16
[patent_title] => Integrated circuit structure with backside via
[patent_app_type] => utility
[patent_app_number] => 17/158409
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 73
[patent_figures_cnt] => 96
[patent_no_of_words] => 16044
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158409
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/158409 | Integrated circuit structure with backside via | Jan 25, 2021 | Issued |
Array
(
[id] => 16951924
[patent_doc_number] => 20210210616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/157180
[patent_app_country] => US
[patent_app_date] => 2021-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9994
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157180
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/157180 | Semiconductor device and method of manufacturing the same | Jan 24, 2021 | Issued |
Array
(
[id] => 17025589
[patent_doc_number] => 20210249461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => INCREASED OPTICAL PATH FOR LONG WAVELENGTH LIGHT BY GRATING STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/156851
[patent_app_country] => US
[patent_app_date] => 2021-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156851
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/156851 | Increased optical path for long wavelength light by grating structure | Jan 24, 2021 | Issued |
Array
(
[id] => 17402918
[patent_doc_number] => 20220045009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => SEMICONDUCTOR DEVICE HAVING WAFER-TO-WAFER BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/148147
[patent_app_country] => US
[patent_app_date] => 2021-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7426
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148147
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148147 | Semiconductor device having wafer-to-wafer bonding structure and manufacturing method thereof | Jan 12, 2021 | Issued |
Array
(
[id] => 17738222
[patent_doc_number] => 20220223684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => Gate Air Spacer Protection During Source/Drain Via Hole Etching
[patent_app_type] => utility
[patent_app_number] => 17/145017
[patent_app_country] => US
[patent_app_date] => 2021-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8586
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145017
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/145017 | Gate air spacer protection during source/drain via hole etching | Jan 7, 2021 | Issued |
Array
(
[id] => 17574074
[patent_doc_number] => 11322348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-03
[patent_title] => Multi-function equipment implementing fabrication of high-k dielectric layer
[patent_app_type] => utility
[patent_app_number] => 17/141935
[patent_app_country] => US
[patent_app_date] => 2021-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4532
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 541
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141935
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/141935 | Multi-function equipment implementing fabrication of high-k dielectric layer | Jan 4, 2021 | Issued |
Array
(
[id] => 16781775
[patent_doc_number] => 20210118854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => THREE-DIMENSIONAL MICROELECTRONIC PACKAGE WITH EMBEDDED COOLING CHANNELS
[patent_app_type] => utility
[patent_app_number] => 17/135474
[patent_app_country] => US
[patent_app_date] => 2020-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7646
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135474
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/135474 | Three-dimensional microelectronic package with embedded cooling channels | Dec 27, 2020 | Issued |
Array
(
[id] => 17692322
[patent_doc_number] => 20220199615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => SUBSTRATE-LESS VERTICAL DIODE INTEGRATED CIRCUIT STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/133024
[patent_app_country] => US
[patent_app_date] => 2020-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17306
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133024
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/133024 | Substrate-less vertical diode integrated circuit structures | Dec 22, 2020 | Issued |