
Dao H. Nguyen
Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2283 |
| Issued Applications | 1976 |
| Pending Applications | 142 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17500672
[patent_doc_number] => 11289382
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => Method for forming transistor with strained channel
[patent_app_type] => utility
[patent_app_number] => 17/121767
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2403
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121767
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/121767 | Method for forming transistor with strained channel | Dec 14, 2020 | Issued |
Array
(
[id] => 17716636
[patent_doc_number] => 11380635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/121898
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8856
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121898
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/121898 | Semiconductor device | Dec 14, 2020 | Issued |
Array
(
[id] => 16752423
[patent_doc_number] => 20210104435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE, AND ASSOCIATED CONFIGURATIONS
[patent_app_type] => utility
[patent_app_number] => 17/122939
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7310
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122939
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/122939 | Techniques for revealing a backside of an integrated circuit device, and associated configurations | Dec 14, 2020 | Issued |
Array
(
[id] => 18236127
[patent_doc_number] => 11600695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Dielectric fins with air gap and backside self-aligned contact
[patent_app_type] => utility
[patent_app_number] => 17/118262
[patent_app_country] => US
[patent_app_date] => 2020-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 101
[patent_no_of_words] => 12980
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/118262 | Dielectric fins with air gap and backside self-aligned contact | Dec 9, 2020 | Issued |
Array
(
[id] => 16723822
[patent_doc_number] => 20210090969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SEMICONDUCTOR ASSEMBLIES INCLUDING VERTICALLY INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/115716
[patent_app_country] => US
[patent_app_date] => 2020-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3913
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115716
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/115716 | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same | Dec 7, 2020 | Issued |
Array
(
[id] => 16889189
[patent_doc_number] => 20210175386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-10
[patent_title] => INTEGRATED MODULE ASSEMBLY FOR OPTICAL INTEGRATED CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/109316
[patent_app_country] => US
[patent_app_date] => 2020-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109316
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/109316 | Integrated module assembly for optical integrated circuits | Dec 1, 2020 | Issued |
Array
(
[id] => 18236126
[patent_doc_number] => 11600694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Integrated circuit device including gate line
[patent_app_type] => utility
[patent_app_number] => 17/106971
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 10233
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106971
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/106971 | Integrated circuit device including gate line | Nov 29, 2020 | Issued |
Array
(
[id] => 18579050
[patent_doc_number] => 11735590
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Fin stack including tensile-strained and compressively strained fin portions
[patent_app_type] => utility
[patent_app_number] => 17/098300
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 34
[patent_no_of_words] => 9327
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098300
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/098300 | Fin stack including tensile-strained and compressively strained fin portions | Nov 12, 2020 | Issued |
Array
(
[id] => 16715674
[patent_doc_number] => 20210082821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES HAVING RAISED VIA CONTACTS
[patent_app_type] => utility
[patent_app_number] => 17/093947
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093947
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/093947 | Methods of fabricating integrated circuit devices having raised via contacts | Nov 9, 2020 | Issued |
Array
(
[id] => 17787809
[patent_doc_number] => 11410945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-09
[patent_title] => Semiconductor package having partial outer metal layer and packaging method thereof
[patent_app_type] => utility
[patent_app_number] => 17/094101
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 26
[patent_no_of_words] => 3639
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094101
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094101 | Semiconductor package having partial outer metal layer and packaging method thereof | Nov 9, 2020 | Issued |
Array
(
[id] => 18796982
[patent_doc_number] => 11830817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-28
[patent_title] => Creating interconnects between dies using a cross-over die and through-die vias
[patent_app_type] => utility
[patent_app_number] => 17/085215
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6831
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085215
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/085215 | Creating interconnects between dies using a cross-over die and through-die vias | Oct 29, 2020 | Issued |
Array
(
[id] => 17745636
[patent_doc_number] => 11393717
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Insulating cap on contact structure and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/078606
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 27
[patent_no_of_words] => 9647
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078606
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/078606 | Insulating cap on contact structure and method for forming the same | Oct 22, 2020 | Issued |
Array
(
[id] => 16625118
[patent_doc_number] => 20210043771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/078856
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078856
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/078856 | Semiconductor device and manufacturing method thereof | Oct 22, 2020 | Issued |
Array
(
[id] => 16625023
[patent_doc_number] => 20210043676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/068783
[patent_app_country] => US
[patent_app_date] => 2020-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17218
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068783
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/068783 | Semiconductor device, solid-state imaging device and electronic apparatus | Oct 11, 2020 | Issued |
Array
(
[id] => 16765716
[patent_doc_number] => 20210111298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => Photodetectors
[patent_app_type] => utility
[patent_app_number] => 17/066735
[patent_app_country] => US
[patent_app_date] => 2020-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5005
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066735
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/066735 | Photodetectors | Oct 8, 2020 | Issued |
Array
(
[id] => 17500785
[patent_doc_number] => 11289495
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-03-29
[patent_title] => Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits
[patent_app_type] => utility
[patent_app_number] => 17/038037
[patent_app_country] => US
[patent_app_date] => 2020-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10237
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038037
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/038037 | Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits | Sep 29, 2020 | Issued |
Array
(
[id] => 18016431
[patent_doc_number] => 11508738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-22
[patent_title] => SRAM speed and margin optimization via spacer tuning
[patent_app_type] => utility
[patent_app_number] => 17/036487
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11180
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036487
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036487 | SRAM speed and margin optimization via spacer tuning | Sep 28, 2020 | Issued |
Array
(
[id] => 16617361
[patent_doc_number] => 20210036014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/034764
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14977
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034764
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/034764 | Three-dimensional semiconductor device | Sep 27, 2020 | Issued |
Array
(
[id] => 17956487
[patent_doc_number] => 11482602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-25
[patent_title] => Semiconductor devices and methods of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/034088
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 53
[patent_no_of_words] => 10343
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034088
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/034088 | Semiconductor devices and methods of fabricating the same | Sep 27, 2020 | Issued |
Array
(
[id] => 18520803
[patent_doc_number] => 11710698
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-25
[patent_title] => Dual-track bitline scheme for 6T SRAM cells
[patent_app_type] => utility
[patent_app_number] => 17/030821
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 7333
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030821
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/030821 | Dual-track bitline scheme for 6T SRAM cells | Sep 23, 2020 | Issued |