Search

Dao H. Nguyen

Examiner (ID: 4524)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2231
Issued Applications
1935
Pending Applications
150
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20245978 [patent_doc_number] => 12426323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor device including vertical transistor with back side power structure [patent_app_type] => utility [patent_app_number] => 18/584387 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584387
Semiconductor device including vertical transistor with back side power structure Feb 21, 2024 Issued
Array ( [id] => 20305402 [patent_doc_number] => 12451401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Thermal dissipation in semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/583411 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 8921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583411 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583411
Thermal dissipation in semiconductor devices Feb 20, 2024 Issued
Array ( [id] => 19844117 [patent_doc_number] => 12256533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Semiconductor memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/427852 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427852
Semiconductor memory device and method of fabricating the same Jan 30, 2024 Issued
Array ( [id] => 19951320 [patent_doc_number] => 12322691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Package structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/420775 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420775 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420775
Package structure and method of manufacturing the same Jan 23, 2024 Issued
Array ( [id] => 19670921 [patent_doc_number] => 12183692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-31 [patent_title] => Embedded inductors and integrated voltage regulators for packaged semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/404535 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404535 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404535
Embedded inductors and integrated voltage regulators for packaged semiconductor devices Jan 3, 2024 Issued
Array ( [id] => 19130867 [patent_doc_number] => 20240136220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => Shallow Trench Isolation Forming Method and Structures Resulting Therefrom [patent_app_type] => utility [patent_app_number] => 18/401955 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401955
Shallow trench isolation forming method and structures resulting therefrom Jan 1, 2024 Issued
Array ( [id] => 19130867 [patent_doc_number] => 20240136220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => Shallow Trench Isolation Forming Method and Structures Resulting Therefrom [patent_app_type] => utility [patent_app_number] => 18/401955 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401955
Shallow trench isolation forming method and structures resulting therefrom Jan 1, 2024 Issued
Array ( [id] => 20405593 [patent_doc_number] => 12495583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Semiconductor arrangement and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/536162 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 1083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536162
Semiconductor arrangement and method of manufacture Dec 10, 2023 Issued
Array ( [id] => 20259088 [patent_doc_number] => 12431453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Electronic device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/530123 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530123
Electronic device package and method for manufacturing the same Dec 4, 2023 Issued
Array ( [id] => 20259088 [patent_doc_number] => 12431453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Electronic device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/530123 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530123
Electronic device package and method for manufacturing the same Dec 4, 2023 Issued
Array ( [id] => 20259088 [patent_doc_number] => 12431453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Electronic device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/530123 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530123
Electronic device package and method for manufacturing the same Dec 4, 2023 Issued
Array ( [id] => 20259088 [patent_doc_number] => 12431453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Electronic device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/530123 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530123
Electronic device package and method for manufacturing the same Dec 4, 2023 Issued
Array ( [id] => 20319212 [patent_doc_number] => 12457774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Multi-gate device and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 18/526856 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 48 [patent_no_of_words] => 5350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526856
Multi-gate device and method of fabrication thereof Nov 30, 2023 Issued
Array ( [id] => 20205654 [patent_doc_number] => 12408451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor device, solid-state imaging device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 18/520273 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 12771 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520273
Semiconductor device, solid-state imaging device and electronic apparatus Nov 26, 2023 Issued
Array ( [id] => 20268611 [patent_doc_number] => 12439623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Field effect transistors with dual silicide contact structures [patent_app_type] => utility [patent_app_number] => 18/516410 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 9132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516410
Field effect transistors with dual silicide contact structures Nov 20, 2023 Issued
Array ( [id] => 20205588 [patent_doc_number] => 12408384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor device and display device including the semiconductor device [patent_app_type] => utility [patent_app_number] => 18/513803 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 164 [patent_no_of_words] => 50396 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513803
Semiconductor device and display device including the semiconductor device Nov 19, 2023 Issued
Array ( [id] => 19007869 [patent_doc_number] => 20240071940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CREATING INTERCONNECTS BETWEEN DIES USING A CROSS-OVER DIE AND THROUGH-DIE VIAS [patent_app_type] => utility [patent_app_number] => 18/505187 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505187
CREATING INTERCONNECTS BETWEEN DIES USING A CROSS-OVER DIE AND THROUGH-DIE VIAS Nov 8, 2023 Pending
Array ( [id] => 19007869 [patent_doc_number] => 20240071940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CREATING INTERCONNECTS BETWEEN DIES USING A CROSS-OVER DIE AND THROUGH-DIE VIAS [patent_app_type] => utility [patent_app_number] => 18/505187 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505187
CREATING INTERCONNECTS BETWEEN DIES USING A CROSS-OVER DIE AND THROUGH-DIE VIAS Nov 8, 2023 Pending
Array ( [id] => 18975430 [patent_doc_number] => 20240055522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => METHOD FOR FORMING VIA STRUCTURE WITH LOW RESISTIVITY [patent_app_type] => utility [patent_app_number] => 18/494376 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494376 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494376
METHOD FOR FORMING VIA STRUCTURE WITH LOW RESISTIVITY Oct 24, 2023 Pending
Array ( [id] => 18975266 [patent_doc_number] => 20240055358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => ELECTRONIC PACKAGE WITH ROTATED SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 18/383466 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383466
Electronic package with rotated semiconductor die Oct 23, 2023 Issued
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