Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16920487 [patent_doc_number] => 20210193579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 16/724907 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724907
Embedded die architecture and method of making Dec 22, 2019 Issued
Array ( [id] => 16920487 [patent_doc_number] => 20210193579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 16/724907 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724907
Embedded die architecture and method of making Dec 22, 2019 Issued
Array ( [id] => 16920487 [patent_doc_number] => 20210193579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 16/724907 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724907
Embedded die architecture and method of making Dec 22, 2019 Issued
Array ( [id] => 16920487 [patent_doc_number] => 20210193579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 16/724907 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724907
Embedded die architecture and method of making Dec 22, 2019 Issued
Array ( [id] => 16911511 [patent_doc_number] => 11043561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Multi-gate device and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 16/723559 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 48 [patent_no_of_words] => 10565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723559
Multi-gate device and method of fabrication thereof Dec 19, 2019 Issued
Array ( [id] => 17366102 [patent_doc_number] => 11233134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Field effect transistors with dual silicide contact structures [patent_app_type] => utility [patent_app_number] => 16/721352 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 13717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721352
Field effect transistors with dual silicide contact structures Dec 18, 2019 Issued
Array ( [id] => 16911445 [patent_doc_number] => 11043495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Integrated circuit semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/718799 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718799
Integrated circuit semiconductor device and method of manufacturing the same Dec 17, 2019 Issued
Array ( [id] => 16759853 [patent_doc_number] => 10978410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/717329 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717329
Semiconductor structure and manufacturing method thereof Dec 16, 2019 Issued
Array ( [id] => 16904881 [patent_doc_number] => 20210183797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => Bottom-Side Heatsinking Waveguide for an Integrated Circuit Package [patent_app_type] => utility [patent_app_number] => 16/716711 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716711
Bottom-side heatsinking waveguide for an integrated circuit package Dec 16, 2019 Issued
Array ( [id] => 15840581 [patent_doc_number] => 20200135573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => STRUCTURE AND METHOD OF FORMING FIN DEVICE HAVING IMPROVED FIN LINER [patent_app_type] => utility [patent_app_number] => 16/714059 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714059
Structure and method of forming fin device having improved fin liner Dec 12, 2019 Issued
Array ( [id] => 15746049 [patent_doc_number] => 20200111914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE, OR DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/704416 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704416
Semiconductor device, manufacturing method of the semiconductor device, or display device including the semiconductor device Dec 4, 2019 Issued
Array ( [id] => 15688205 [patent_doc_number] => 20200098766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => Fin-Based Strap Cell Structure for Improving Memory Performance [patent_app_type] => utility [patent_app_number] => 16/696999 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696999
Fin-based strap cell structure for improving memory performance Nov 25, 2019 Issued
Array ( [id] => 16858467 [patent_doc_number] => 20210159212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => INDUCTOR DESIGN IN ACTIVE 3D STACKING TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 16/694476 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694476
Inductor design in active 3D stacking technology Nov 24, 2019 Issued
Array ( [id] => 15656983 [patent_doc_number] => 20200091022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/690711 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690711
Semiconductor structure with conductive structure Nov 20, 2019 Issued
Array ( [id] => 15939427 [patent_doc_number] => 20200161347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/688234 [patent_app_country] => US [patent_app_date] => 2019-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16688234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/688234
Image pickup device and electronic apparatus Nov 18, 2019 Issued
Array ( [id] => 15625441 [patent_doc_number] => 20200083125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/683619 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683619
Semiconductor structure with conductive structure Nov 13, 2019 Issued
Array ( [id] => 16000903 [patent_doc_number] => 20200176322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 16/682163 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682163 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682163
Semiconductor device and method of manufacture Nov 12, 2019 Issued
Array ( [id] => 16653499 [patent_doc_number] => 10930692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Increased optical path for long wavelength light by grating structure [patent_app_type] => utility [patent_app_number] => 16/672814 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 7682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672814
Increased optical path for long wavelength light by grating structure Nov 3, 2019 Issued
Array ( [id] => 16812196 [patent_doc_number] => 20210134751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/673699 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673699
Electronic device package and method for manufacturing the same Nov 3, 2019 Issued
Array ( [id] => 16881222 [patent_doc_number] => 11031379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Stray inductance reduction in packaged semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/671450 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671450
Stray inductance reduction in packaged semiconductor devices Oct 31, 2019 Issued
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