Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16724057 [patent_doc_number] => 20210091204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => FERROELECTRIC MEMORY DEVICES WITH DUAL DIELECTRIC CONFINEMENT AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/577176 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577176 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577176
Ferroelectric memory devices with dual dielectric confinement and methods of forming the same Sep 19, 2019 Issued
Array ( [id] => 17607104 [patent_doc_number] => 11335596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Selective deposition for integrated circuit interconnect structures [patent_app_type] => utility [patent_app_number] => 16/577079 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577079
Selective deposition for integrated circuit interconnect structures Sep 19, 2019 Issued
Array ( [id] => 15717685 [patent_doc_number] => 20200105610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MAKING [patent_app_type] => utility [patent_app_number] => 16/577377 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577377
Semiconductor arrangement and method for making Sep 19, 2019 Issued
Array ( [id] => 15922411 [patent_doc_number] => 10658454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Capacitor, semiconductor device and methods of manufacturing the capacitor and the semiconductor device [patent_app_type] => utility [patent_app_number] => 16/573156 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 12591 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573156
Capacitor, semiconductor device and methods of manufacturing the capacitor and the semiconductor device Sep 16, 2019 Issued
Array ( [id] => 15597899 [patent_doc_number] => 20200075484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => Semiconductor Package and Method of Manufacturing a Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/560139 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560139
Semiconductor package and method of manufacturing a semiconductor package Sep 3, 2019 Issued
Array ( [id] => 15717807 [patent_doc_number] => 20200105671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => HYBRID POWER RAIL STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/559547 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559547
Hybrid power rail structure Sep 2, 2019 Issued
Array ( [id] => 15443121 [patent_doc_number] => 20200035744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/555067 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555067
Semiconductor device, solid-state imaging device and electronic apparatus Aug 28, 2019 Issued
Array ( [id] => 17232603 [patent_doc_number] => 20210359160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => USING A COMPLIANT LAYER TO ELIMINATE BUMP BONDING [patent_app_type] => utility [patent_app_number] => 17/297708 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17297708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/297708
Using a compliant layer to eliminate bump bonding Aug 21, 2019 Issued
Array ( [id] => 16272315 [patent_doc_number] => 20200273803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/513726 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513726
Semiconductor package and manufacturing method thereof Jul 16, 2019 Issued
Array ( [id] => 16586157 [patent_doc_number] => 20210020559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/513727 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513727
Semiconductor package and manufacturing method thereof Jul 16, 2019 Issued
Array ( [id] => 16586158 [patent_doc_number] => 20210020560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/513730 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513730
Package structure and method of manufacturing the same Jul 16, 2019 Issued
Array ( [id] => 16516155 [patent_doc_number] => 20200395413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => MEMORY CELL AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/513719 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513719 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513719
Memory cell and forming method thereof Jul 16, 2019 Issued
Array ( [id] => 16819958 [patent_doc_number] => 11004796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Integrated fan-out package [patent_app_type] => utility [patent_app_number] => 16/513729 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 7558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513729 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513729
Integrated fan-out package Jul 16, 2019 Issued
Array ( [id] => 17683363 [patent_doc_number] => 11367628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Molded chip package with anchor structures [patent_app_type] => utility [patent_app_number] => 16/513450 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 5108 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513450
Molded chip package with anchor structures Jul 15, 2019 Issued
Array ( [id] => 16739130 [patent_doc_number] => 10964798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/512326 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 45 [patent_no_of_words] => 9903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512326
Semiconductor device and method of manufacturing the same Jul 14, 2019 Issued
Array ( [id] => 16928344 [patent_doc_number] => 11049835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Semiconductor module [patent_app_type] => utility [patent_app_number] => 16/508739 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7632 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508739
Semiconductor module Jul 10, 2019 Issued
Array ( [id] => 16521610 [patent_doc_number] => 10872835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-22 [patent_title] => Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/503363 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503363
Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same Jul 2, 2019 Issued
Array ( [id] => 16560612 [patent_doc_number] => 20210005761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/503318 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503318 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503318
Optical device and method of manufacturing the same Jul 2, 2019 Issued
Array ( [id] => 15717521 [patent_doc_number] => 20200105528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SELF ALIGNED LITHO ETCH PROCESS PATTERNING METHOD [patent_app_type] => utility [patent_app_number] => 16/503277 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503277
Self aligned litho etch process patterning method Jul 2, 2019 Issued
Array ( [id] => 16560396 [patent_doc_number] => 20210005545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => INTEGRATED DEVICES COMPRISING UNIFORM METAL LAYER THICKNESS ACROSS ONE OR MORE METAL LAYERS [patent_app_type] => utility [patent_app_number] => 16/503237 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503237
INTEGRATED DEVICES COMPRISING UNIFORM METAL LAYER THICKNESS ACROSS ONE OR MORE METAL LAYERS Jul 2, 2019 Abandoned
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