Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16692225 [patent_doc_number] => 20210074704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => BOTTOM FIN TRIM ISOLATION ALIGNED WITH TOP GATE FOR STACKED DEVICE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 16/650155 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/650155
Bottom fin trim isolation aligned with top gate for stacked device architectures Jan 9, 2018 Issued
Array ( [id] => 16163163 [patent_doc_number] => 20200219814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => ZERO-MISALIGNMENT TWO-VIA STRUCTURES USING PHOTOIMAGEABLE DIELECTRIC FILM BUILDUP FILM, AND TRANSPARENT SUBSTRATE WITH ELECTROLESS PLATING [patent_app_type] => utility [patent_app_number] => 16/648640 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16648640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/648640
Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating Dec 29, 2017 Issued
Array ( [id] => 14617059 [patent_doc_number] => 10361237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Low dark current backside illumination sensor [patent_app_type] => utility [patent_app_number] => 15/855307 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3921 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855307
Low dark current backside illumination sensor Dec 26, 2017 Issued
Array ( [id] => 14460075 [patent_doc_number] => 10326012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Nitride semiconductor device [patent_app_type] => utility [patent_app_number] => 15/855261 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4167 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855261
Nitride semiconductor device Dec 26, 2017 Issued
Array ( [id] => 13229037 [patent_doc_number] => 10128301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Semiconductor device, solid-state imaging device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 15/852468 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 17149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852468 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852468
Semiconductor device, solid-state imaging device and electronic apparatus Dec 21, 2017 Issued
Array ( [id] => 13334863 [patent_doc_number] => 20180218969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/850009 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 661 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850009
Semiconductor device Dec 20, 2017 Issued
Array ( [id] => 13921425 [patent_doc_number] => 10204836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Porous silicon relaxation medium for dislocation free CMOS devices [patent_app_type] => utility [patent_app_number] => 15/850643 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4292 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850643
Porous silicon relaxation medium for dislocation free CMOS devices Dec 20, 2017 Issued
Array ( [id] => 14350913 [patent_doc_number] => 20190157429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => BACK-CHANNEL-ETCHED TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/749095 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/749095
BACK-CHANNEL-ETCHED TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF Dec 19, 2017 Abandoned
Array ( [id] => 14036203 [patent_doc_number] => 10229857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Porous silicon relaxation medium for dislocation free CMOS devices [patent_app_type] => utility [patent_app_number] => 15/846968 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4284 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846968
Porous silicon relaxation medium for dislocation free CMOS devices Dec 18, 2017 Issued
Array ( [id] => 13085337 [patent_doc_number] => 10062742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/845459 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 48 [patent_no_of_words] => 12682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845459
Semiconductor device Dec 17, 2017 Issued
Array ( [id] => 12823720 [patent_doc_number] => 20180166412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 15/837560 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837560
Semiconductor module Dec 10, 2017 Issued
Array ( [id] => 14151985 [patent_doc_number] => 10256382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Collimated OLED light field display [patent_app_type] => utility [patent_app_number] => 15/837654 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5094 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837654
Collimated OLED light field display Dec 10, 2017 Issued
Array ( [id] => 14446485 [patent_doc_number] => 20190181116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => FAN-OUT STRUCTURE FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/837857 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837857 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837857
FAN-OUT STRUCTURE FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS Dec 10, 2017 Abandoned
Array ( [id] => 13132339 [patent_doc_number] => 10084109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-25 [patent_title] => Semiconductor structure for improving the gate adhesion and Schottky stability [patent_app_type] => utility [patent_app_number] => 15/837673 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2118 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837673
Semiconductor structure for improving the gate adhesion and Schottky stability Dec 10, 2017 Issued
Array ( [id] => 15475329 [patent_doc_number] => 10553549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Cavity formation in backside interface layer for radio-frequency isolation [patent_app_type] => utility [patent_app_number] => 15/833175 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 148 [patent_no_of_words] => 26581 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833175 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/833175
Cavity formation in backside interface layer for radio-frequency isolation Dec 5, 2017 Issued
Array ( [id] => 16324230 [patent_doc_number] => 10784202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => High-density chip-to-chip interconnection with silicon bridge [patent_app_type] => utility [patent_app_number] => 15/828463 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2910 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/828463
High-density chip-to-chip interconnection with silicon bridge Nov 30, 2017 Issued
Array ( [id] => 14178199 [patent_doc_number] => 10263122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor [patent_app_type] => utility [patent_app_number] => 15/828386 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 6850 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/828386
Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor Nov 29, 2017 Issued
Array ( [id] => 12595803 [patent_doc_number] => 20180090431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/817281 [patent_app_country] => US [patent_app_date] => 2017-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817281
Semiconductor structure Nov 18, 2017 Issued
Array ( [id] => 13334881 [patent_doc_number] => 20180218978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => VERTICALLY INTEGRATED NANOSHEET FUSE [patent_app_type] => utility [patent_app_number] => 15/810940 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810940
Vertically integrated nanosheet fuse Nov 12, 2017 Issued
Array ( [id] => 14309123 [patent_doc_number] => 20190144265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => WAFER LEVEL PACKAGING FOR MEMS DEVICE [patent_app_type] => utility [patent_app_number] => 15/810163 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810163
Wafer level packaging for MEMS device Nov 12, 2017 Issued
Menu