Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12849241 [patent_doc_number] => 20180174920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/651018 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651018
Semiconductor devices Jul 16, 2017 Issued
Array ( [id] => 12223543 [patent_doc_number] => 20180061903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING FLEXIBLE DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/651193 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651193 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651193
Flexible display apparatus and method of manufacturing flexible display apparatus Jul 16, 2017 Issued
Array ( [id] => 12778903 [patent_doc_number] => 20180151469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SOLID-STATE DRIVE DEVICE [patent_app_type] => utility [patent_app_number] => 15/651106 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651106
Solid-state drive device Jul 16, 2017 Issued
Array ( [id] => 12290019 [patent_doc_number] => 09933678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-03 [patent_title] => Active element array substrate and display panel using the same [patent_app_type] => utility [patent_app_number] => 15/651054 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6660 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651054 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651054
Active element array substrate and display panel using the same Jul 16, 2017 Issued
Array ( [id] => 12122437 [patent_doc_number] => 20180006022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => '3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR' [patent_app_type] => utility [patent_app_number] => 15/650530 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650530 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650530
3D bonded semiconductor structure with an embedded capacitor Jul 13, 2017 Issued
Array ( [id] => 13085149 [patent_doc_number] => 10062647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Interconnect structure having tungsten contact copper wiring [patent_app_type] => utility [patent_app_number] => 15/646325 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4354 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/646325
Interconnect structure having tungsten contact copper wiring Jul 10, 2017 Issued
Array ( [id] => 15000105 [patent_doc_number] => 20190319010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/314485 [patent_app_country] => US [patent_app_date] => 2017-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16314485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/314485
Semiconductor packaging structure and method of forming the same Jul 2, 2017 Issued
Array ( [id] => 11983722 [patent_doc_number] => 20170287877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR PACKAGE ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/624790 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3197 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624790
Semiconductor package assembly Jun 15, 2017 Issued
Array ( [id] => 11974678 [patent_doc_number] => 20170278832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'SEMICONDUCTOR PACKAGE ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/618210 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15618210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/618210
Semiconductor package assembly Jun 8, 2017 Issued
Array ( [id] => 13159919 [patent_doc_number] => 10096695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Closely packed vertical transistors with reduced contact resistance [patent_app_type] => utility [patent_app_number] => 15/618611 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5325 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15618611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/618611
Closely packed vertical transistors with reduced contact resistance Jun 8, 2017 Issued
Array ( [id] => 11967345 [patent_doc_number] => 20170271498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR DEVICE WITH NON-UNIFORM TRENCH OXIDE LAYER' [patent_app_type] => utility [patent_app_number] => 15/614257 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5385 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614257
Semiconductor device with non-uniform trench oxide layer Jun 4, 2017 Issued
Array ( [id] => 12416970 [patent_doc_number] => 09972606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding [patent_app_type] => utility [patent_app_number] => 15/604803 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604803
Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding May 24, 2017 Issued
Array ( [id] => 13201589 [patent_doc_number] => 10115715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Methods of making semiconductor device packages and related semiconductor device packages [patent_app_type] => utility [patent_app_number] => 15/602759 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602759 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/602759
Methods of making semiconductor device packages and related semiconductor device packages May 22, 2017 Issued
Array ( [id] => 13243263 [patent_doc_number] => 10134843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Multi-gate device and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 15/600441 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 48 [patent_no_of_words] => 10519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600441 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600441
Multi-gate device and method of fabrication thereof May 18, 2017 Issued
Array ( [id] => 13543605 [patent_doc_number] => 20180323349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => LIGHT-EMITTING DEVICE PACKAGE AND LIGHTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/775912 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775912
Light-emitting device package and lighting device May 15, 2017 Issued
Array ( [id] => 12223632 [patent_doc_number] => 20180061992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/591239 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591239 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/591239
Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors May 9, 2017 Issued
Array ( [id] => 13057493 [patent_doc_number] => 10050148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 15/589777 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 5462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589777 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589777
Semiconductor device and method of forming the same May 7, 2017 Issued
Array ( [id] => 14509639 [patent_doc_number] => 20190198474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MULTIPLE SIZED BUMP BONDS [patent_app_type] => utility [patent_app_number] => 15/498613 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/498613
MULTIPLE SIZED BUMP BONDS Apr 26, 2017 Abandoned
Array ( [id] => 12229736 [patent_doc_number] => 09916984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Self-aligned source and drain regions for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 15/483273 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483273
Self-aligned source and drain regions for semiconductor devices Apr 9, 2017 Issued
Array ( [id] => 12417213 [patent_doc_number] => 09972687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-15 [patent_title] => High quality vanadium dioxide films [patent_app_type] => utility [patent_app_number] => 15/464536 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5282 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464536
High quality vanadium dioxide films Mar 20, 2017 Issued
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