
Dao H. Nguyen
Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2283 |
| Issued Applications | 1976 |
| Pending Applications | 142 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12202571
[patent_doc_number] => 09905643
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[patent_title] => 'Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors'
[patent_app_type] => utility
[patent_app_number] => 15/248237
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Array
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[patent_title] => 'Closely packed vertical transistors with reduced contact resistance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/248355 | Closely packed vertical transistors with reduced contact resistance | Aug 25, 2016 | Issued |
Array
(
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[patent_title] => 'Display'
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Array
(
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[patent_doc_number] => 20180241142
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[patent_kind] => A1
[patent_issue_date] => 2018-08-23
[patent_title] => ELECTRICAL CONTACT TERMINAL AND ELECTRONIC COMPONENT SOCKET
[patent_app_type] => utility
[patent_app_number] => 15/755040
[patent_app_country] => US
[patent_app_date] => 2016-08-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/755040 | Electrical contact terminal and electronic component socket | Aug 15, 2016 | Issued |
Array
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[patent_title] => 'Directly forming SiGe fins on oxide'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/229754 | Directly forming SiGe fins on oxide | Aug 4, 2016 | Issued |
Array
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[patent_doc_number] => 09773978
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[patent_issue_date] => 2017-09-26
[patent_title] => 'Optimal device structures for back-end-of-line compatible mixed ionic electronic conductors materials'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/225914 | Optimal device structures for back-end-of-line compatible mixed ionic electronic conductors materials | Aug 1, 2016 | Issued |
Array
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[patent_issue_date] => 2018-06-19
[patent_title] => Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
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Array
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[id] => 12061881
[patent_doc_number] => 20170338225
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[patent_issue_date] => 2017-11-23
[patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING FINS AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/226007
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/226007 | Semiconductor structure having fins and method for manufacturing the same | Aug 1, 2016 | Issued |
Array
(
[id] => 11811531
[patent_doc_number] => 09716105
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[patent_issue_date] => 2017-07-25
[patent_title] => 'Three-dimensional memory device with different thickness insulating layers and method of making thereof'
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Array
(
[id] => 11652869
[patent_doc_number] => 20170148771
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[patent_issue_date] => 2017-05-25
[patent_title] => 'LIGHT SOURCE MODULE, DISPLAY PANEL, AND DISPLAY APPARATUS INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/226209
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/226209 | Light source module, display panel, and display apparatus including the same | Aug 1, 2016 | Issued |
Array
(
[id] => 11483415
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[patent_title] => 'Antifuse one-time programmable memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/225842 | Antifuse one-time programmable memory | Aug 1, 2016 | Issued |
Array
(
[id] => 11967202
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Array
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[patent_title] => Metal Gate Isolation Structure and Method Forming Same
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/225304 | Metal gate isolation structure and method forming same | Jul 31, 2016 | Issued |
Array
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Array
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Array
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[patent_title] => LOW NOISE AND HIGH PERFORMANCE LSI DEVICE
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Array
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