Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12202571 [patent_doc_number] => 09905643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors' [patent_app_type] => utility [patent_app_number] => 15/248237 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5702 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248237
Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors Aug 25, 2016 Issued
Array ( [id] => 11847694 [patent_doc_number] => 09735253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'Closely packed vertical transistors with reduced contact resistance' [patent_app_type] => utility [patent_app_number] => 15/248355 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5480 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248355
Closely packed vertical transistors with reduced contact resistance Aug 25, 2016 Issued
Array ( [id] => 12213396 [patent_doc_number] => 09910199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Display' [patent_app_type] => utility [patent_app_number] => 15/241518 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 50 [patent_no_of_words] => 12248 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/241518
Display Aug 18, 2016 Issued
Array ( [id] => 13379201 [patent_doc_number] => 20180241142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => ELECTRICAL CONTACT TERMINAL AND ELECTRONIC COMPONENT SOCKET [patent_app_type] => utility [patent_app_number] => 15/755040 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15755040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/755040
Electrical contact terminal and electronic component socket Aug 15, 2016 Issued
Array ( [id] => 11811472 [patent_doc_number] => 09716045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Directly forming SiGe fins on oxide' [patent_app_type] => utility [patent_app_number] => 15/229754 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229754 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/229754
Directly forming SiGe fins on oxide Aug 4, 2016 Issued
Array ( [id] => 11904535 [patent_doc_number] => 09773978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Optimal device structures for back-end-of-line compatible mixed ionic electronic conductors materials' [patent_app_type] => utility [patent_app_number] => 15/225914 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5419 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225914
Optimal device structures for back-end-of-line compatible mixed ionic electronic conductors materials Aug 1, 2016 Issued
Array ( [id] => 12516168 [patent_doc_number] => 10002857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer [patent_app_type] => utility [patent_app_number] => 15/225910 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 11463 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225910
Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer Aug 1, 2016 Issued
Array ( [id] => 12061881 [patent_doc_number] => 20170338225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING FINS AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/226007 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226007 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/226007
Semiconductor structure having fins and method for manufacturing the same Aug 1, 2016 Issued
Array ( [id] => 11811531 [patent_doc_number] => 09716105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Three-dimensional memory device with different thickness insulating layers and method of making thereof' [patent_app_type] => utility [patent_app_number] => 15/226132 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 15689 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/226132
Three-dimensional memory device with different thickness insulating layers and method of making thereof Aug 1, 2016 Issued
Array ( [id] => 11652869 [patent_doc_number] => 20170148771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'LIGHT SOURCE MODULE, DISPLAY PANEL, AND DISPLAY APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/226209 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12423 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/226209
Light source module, display panel, and display apparatus including the same Aug 1, 2016 Issued
Array ( [id] => 11483415 [patent_doc_number] => 09589970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Antifuse one-time programmable memory' [patent_app_type] => utility [patent_app_number] => 15/225842 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225842
Antifuse one-time programmable memory Aug 1, 2016 Issued
Array ( [id] => 11967202 [patent_doc_number] => 20170271355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/225275 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5672 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225275 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225275
Semiconductor memory device and method for manufacturing same Jul 31, 2016 Issued
Array ( [id] => 12990232 [patent_doc_number] => 20170345820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => Metal Gate Isolation Structure and Method Forming Same [patent_app_type] => utility [patent_app_number] => 15/225304 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225304
Metal gate isolation structure and method forming same Jul 31, 2016 Issued
Array ( [id] => 11660276 [patent_doc_number] => 09673290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Self-aligned source and drain regions for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 15/223988 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4273 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15223988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/223988
Self-aligned source and drain regions for semiconductor devices Jul 28, 2016 Issued
Array ( [id] => 11918563 [patent_doc_number] => 09786756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Self-aligned source and drain regions for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 15/224035 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4273 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224035
Self-aligned source and drain regions for semiconductor devices Jul 28, 2016 Issued
Array ( [id] => 11701977 [patent_doc_number] => 09691904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/221656 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 21225 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15221656 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/221656
Semiconductor device Jul 27, 2016 Issued
Array ( [id] => 13682487 [patent_doc_number] => 20160379980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => LOW NOISE AND HIGH PERFORMANCE LSI DEVICE [patent_app_type] => utility [patent_app_number] => 15/211012 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15211012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/211012
Low noise and high performance LSI device Jul 14, 2016 Issued
Array ( [id] => 11681561 [patent_doc_number] => 09680096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Tunable voltage margin access diodes' [patent_app_type] => utility [patent_app_number] => 15/211013 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3083 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15211013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/211013
Tunable voltage margin access diodes Jul 14, 2016 Issued
Array ( [id] => 13976847 [patent_doc_number] => 10217792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip [patent_app_type] => utility [patent_app_number] => 15/739102 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/739102
Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip Jul 10, 2016 Issued
Array ( [id] => 13976847 [patent_doc_number] => 10217792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip [patent_app_type] => utility [patent_app_number] => 15/739102 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/739102
Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip Jul 10, 2016 Issued
Menu