Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 10754337 [patent_doc_number] => 20160100489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/872910 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872910
Method for manufacturing an integrated circuit package Sep 30, 2015 Issued
Array ( [id] => 12650262 [patent_doc_number] => 20180108585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => CHIP PACKAGING STRUCTURE AND PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/573679 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15573679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/573679
CHIP PACKAGING STRUCTURE AND PACKAGING METHOD Sep 15, 2015 Abandoned
Array ( [id] => 10659613 [patent_doc_number] => 20160005757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/854500 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 16741 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854500
Nonvolatile semiconductor memory device and method of manufacturing the same Sep 14, 2015 Issued
Array ( [id] => 12714046 [patent_doc_number] => 20180129848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => CHIP PACKAGING STRUCTURE AND PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/573552 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15573552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/573552
CHIP PACKAGING STRUCTURE AND PACKAGING METHOD Sep 14, 2015 Abandoned
Array ( [id] => 10495329 [patent_doc_number] => 20150380351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Capacitor in Post-Passivation Structures and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/851828 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851828 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851828
Capacitor in post-passivation structures and methods of forming the same Sep 10, 2015 Issued
Array ( [id] => 10479595 [patent_doc_number] => 20150364612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION' [patent_app_type] => utility [patent_app_number] => 14/834306 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834306 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834306
Method of fabricating a GaN P-i-N diode using implantation Aug 23, 2015 Issued
Array ( [id] => 10525623 [patent_doc_number] => 09252143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Radio frequency and microwave devices and methods of use' [patent_app_type] => utility [patent_app_number] => 14/827240 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 7301 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827240 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827240
Radio frequency and microwave devices and methods of use Aug 13, 2015 Issued
Array ( [id] => 10455498 [patent_doc_number] => 20150340514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE' [patent_app_type] => utility [patent_app_number] => 14/813771 [patent_app_country] => US [patent_app_date] => 2015-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/813771
METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE Jul 29, 2015 Abandoned
Array ( [id] => 10689543 [patent_doc_number] => 20160035689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'CHIP INTEGRATION MODULE, CHIP PACKAGE STRUCTURE, AND CHIP INTEGRATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/810043 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810043
CHIP INTEGRATION MODULE, CHIP PACKAGE STRUCTURE, AND CHIP INTEGRATION METHOD Jul 26, 2015 Abandoned
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