
Dao H. Nguyen
Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2283 |
| Issued Applications | 1976 |
| Pending Applications | 142 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8176995
[patent_doc_number] => 08178409
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-15
[patent_title] => 'Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/832963
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/08/178/08178409.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/832963 | Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same | Jul 7, 2010 | Issued |
Array
(
[id] => 8470429
[patent_doc_number] => 08299608
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[patent_kind] => B2
[patent_issue_date] => 2012-10-30
[patent_title] => 'Enhanced thermal management of 3-D stacked die packaging'
[patent_app_type] => utility
[patent_app_number] => 12/832732
[patent_app_country] => US
[patent_app_date] => 2010-07-08
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Array
(
[id] => 8713777
[patent_doc_number] => 08399919
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[patent_kind] => B2
[patent_issue_date] => 2013-03-19
[patent_title] => 'Unit block circuit of semiconductor device'
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[patent_app_number] => 12/832397
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/832397 | Unit block circuit of semiconductor device | Jul 7, 2010 | Issued |
Array
(
[id] => 6193079
[patent_doc_number] => 20110024833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/832748
[patent_app_country] => US
[patent_app_date] => 2010-07-08
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/832748 | Semiconductor device with buried gate and method for fabricating the same | Jul 7, 2010 | Issued |
Array
(
[id] => 8549217
[patent_doc_number] => 08324098
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[patent_issue_date] => 2012-12-04
[patent_title] => 'Via and method of forming the via with a substantially planar top surface that is suitable for carbon nanotube applications'
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[patent_app_number] => 12/832516
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/832516 | Via and method of forming the via with a substantially planar top surface that is suitable for carbon nanotube applications | Jul 7, 2010 | Issued |
Array
(
[id] => 7717187
[patent_doc_number] => 20120007232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-12
[patent_title] => 'MICROELECTRONIC PACKAGES WITH DUAL OR MULTIPLE-ETCHED FLIP-CHIP CONNECTORS'
[patent_app_type] => utility
[patent_app_number] => 12/832376
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/832376 | Microelectronic packages with dual or multiple-etched flip-chip connectors | Jul 7, 2010 | Issued |
Array
(
[id] => 9010033
[patent_doc_number] => 08525335
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[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/828492
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/828492 | Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof | Jun 30, 2010 | Issued |
Array
(
[id] => 8154511
[patent_doc_number] => 20120097921
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[patent_issue_date] => 2012-04-26
[patent_title] => 'Cadmium-free Re-Emitting Semiconductor Construction'
[patent_app_type] => utility
[patent_app_number] => 13/379858
[patent_app_country] => US
[patent_app_date] => 2010-06-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/379858 | Cadmium-free re-emitting semiconductor construction | Jun 24, 2010 | Issued |
Array
(
[id] => 8897145
[patent_doc_number] => 08476668
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[patent_title] => 'High voltage low current surface emitting LED'
[patent_app_type] => utility
[patent_app_number] => 12/814241
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/814241 | High voltage low current surface emitting LED | Jun 10, 2010 | Issued |
Array
(
[id] => 8690372
[patent_doc_number] => 08389901
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-03-05
[patent_title] => 'Welding wire guiding liner'
[patent_app_type] => utility
[patent_app_number] => 12/789095
[patent_app_country] => US
[patent_app_date] => 2010-05-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/789095 | Welding wire guiding liner | May 26, 2010 | Issued |
Array
(
[id] => 8664790
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[patent_issue_date] => 2013-02-19
[patent_title] => 'Method and apparatus for hybrid resolution feedback of a motion stage'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/788583 | Method and apparatus for hybrid resolution feedback of a motion stage | May 26, 2010 | Issued |
Array
(
[id] => 7583761
[patent_doc_number] => 20110278271
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[patent_kind] => A1
[patent_issue_date] => 2011-11-17
[patent_title] => 'SYSTEM AND METHOD FOR LASER SHOCK PEENING'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/778371 | System and method for laser shock peening | May 11, 2010 | Issued |
Array
(
[id] => 8340487
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Array
(
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[patent_title] => 'CONSTRUCT WITH LOCATING FEATURE'
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/717012 | Thermally enhanced thin semiconductor package | Mar 2, 2010 | Issued |