Search

Dao H. Nguyen

Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2283
Issued Applications
1976
Pending Applications
142
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8176995 [patent_doc_number] => 08178409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/832963 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4418 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178409.pdf [firstpage_image] =>[orig_patent_app_number] => 12832963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832963
Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same Jul 7, 2010 Issued
Array ( [id] => 8470429 [patent_doc_number] => 08299608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Enhanced thermal management of 3-D stacked die packaging' [patent_app_type] => utility [patent_app_number] => 12/832732 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3234 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12832732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832732
Enhanced thermal management of 3-D stacked die packaging Jul 7, 2010 Issued
Array ( [id] => 8713777 [patent_doc_number] => 08399919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Unit block circuit of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/832397 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3247 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12832397 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832397
Unit block circuit of semiconductor device Jul 7, 2010 Issued
Array ( [id] => 6193079 [patent_doc_number] => 20110024833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/832748 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6037 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20110024833.pdf [firstpage_image] =>[orig_patent_app_number] => 12832748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832748
Semiconductor device with buried gate and method for fabricating the same Jul 7, 2010 Issued
Array ( [id] => 8549217 [patent_doc_number] => 08324098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Via and method of forming the via with a substantially planar top surface that is suitable for carbon nanotube applications' [patent_app_type] => utility [patent_app_number] => 12/832516 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12832516 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832516
Via and method of forming the via with a substantially planar top surface that is suitable for carbon nanotube applications Jul 7, 2010 Issued
Array ( [id] => 7717187 [patent_doc_number] => 20120007232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'MICROELECTRONIC PACKAGES WITH DUAL OR MULTIPLE-ETCHED FLIP-CHIP CONNECTORS' [patent_app_type] => utility [patent_app_number] => 12/832376 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16894 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20120007232.pdf [firstpage_image] =>[orig_patent_app_number] => 12832376 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832376
Microelectronic packages with dual or multiple-etched flip-chip connectors Jul 7, 2010 Issued
Array ( [id] => 9010033 [patent_doc_number] => 08525335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/828492 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 61 [patent_no_of_words] => 15778 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12828492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/828492
Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof Jun 30, 2010 Issued
Array ( [id] => 8154511 [patent_doc_number] => 20120097921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Cadmium-free Re-Emitting Semiconductor Construction' [patent_app_type] => utility [patent_app_number] => 13/379858 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10076 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20120097921.pdf [firstpage_image] =>[orig_patent_app_number] => 13379858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/379858
Cadmium-free re-emitting semiconductor construction Jun 24, 2010 Issued
Array ( [id] => 8897145 [patent_doc_number] => 08476668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'High voltage low current surface emitting LED' [patent_app_type] => utility [patent_app_number] => 12/814241 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 11306 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12814241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/814241
High voltage low current surface emitting LED Jun 10, 2010 Issued
Array ( [id] => 8690372 [patent_doc_number] => 08389901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-05 [patent_title] => 'Welding wire guiding liner' [patent_app_type] => utility [patent_app_number] => 12/789095 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 30 [patent_no_of_words] => 3470 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789095 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789095
Welding wire guiding liner May 26, 2010 Issued
Array ( [id] => 8664790 [patent_doc_number] => 08378252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method and apparatus for hybrid resolution feedback of a motion stage' [patent_app_type] => utility [patent_app_number] => 12/788583 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2028 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12788583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788583
Method and apparatus for hybrid resolution feedback of a motion stage May 26, 2010 Issued
Array ( [id] => 7583761 [patent_doc_number] => 20110278271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'SYSTEM AND METHOD FOR LASER SHOCK PEENING' [patent_app_type] => utility [patent_app_number] => 12/778371 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20110278271.pdf [firstpage_image] =>[orig_patent_app_number] => 12778371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778371
System and method for laser shock peening May 11, 2010 Issued
Array ( [id] => 8340487 [patent_doc_number] => 08242410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Welding methods and systems' [patent_app_type] => utility [patent_app_number] => 12/775919 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 14715 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12775919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775919
Welding methods and systems May 6, 2010 Issued
Array ( [id] => 6435766 [patent_doc_number] => 20100278990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'CONSTRUCT WITH LOCATING FEATURE' [patent_app_type] => utility [patent_app_number] => 12/771099 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4730 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20100278990.pdf [firstpage_image] =>[orig_patent_app_number] => 12771099 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771099
Construct with locating feature Apr 29, 2010 Issued
Array ( [id] => 7503308 [patent_doc_number] => 08034684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Semiconductor device with improved overlay margin and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/769866 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 6203 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/034/08034684.pdf [firstpage_image] =>[orig_patent_app_number] => 12769866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/769866
Semiconductor device with improved overlay margin and method of manufacturing the same Apr 28, 2010 Issued
Array ( [id] => 6529540 [patent_doc_number] => 20100270294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Vented Susceptor Structure' [patent_app_type] => utility [patent_app_number] => 12/766983 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20100270294.pdf [firstpage_image] =>[orig_patent_app_number] => 12766983 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766983
Vented susceptor structure Apr 25, 2010 Issued
Array ( [id] => 6230636 [patent_doc_number] => 20100264135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Multilayer Susceptor Structure' [patent_app_type] => utility [patent_app_number] => 12/762417 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264135.pdf [firstpage_image] =>[orig_patent_app_number] => 12762417 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762417
Multilayer susceptor structure Apr 18, 2010 Issued
Array ( [id] => 4445791 [patent_doc_number] => 07863609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Compound semiconductor substrate, semiconductor device, and processes for producing them' [patent_app_type] => utility [patent_app_number] => 12/753535 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14955 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863609.pdf [firstpage_image] =>[orig_patent_app_number] => 12753535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753535
Compound semiconductor substrate, semiconductor device, and processes for producing them Apr 1, 2010 Issued
Array ( [id] => 4495843 [patent_doc_number] => 07956376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Light emitting device, method for manufacturing light emitting device, and light emitting apparatus' [patent_app_type] => utility [patent_app_number] => 12/720385 [patent_app_country] => US [patent_app_date] => 2010-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4626 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/956/07956376.pdf [firstpage_image] =>[orig_patent_app_number] => 12720385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/720385
Light emitting device, method for manufacturing light emitting device, and light emitting apparatus Mar 8, 2010 Issued
Array ( [id] => 6280546 [patent_doc_number] => 20100155913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/717012 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4704 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155913.pdf [firstpage_image] =>[orig_patent_app_number] => 12717012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717012
Thermally enhanced thin semiconductor package Mar 2, 2010 Issued
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