
Dao H. Nguyen
Examiner (ID: 14112, Phone: (571)272-1791 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2283 |
| Issued Applications | 1976 |
| Pending Applications | 142 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5026224
[patent_doc_number] => 20070267670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-22
[patent_title] => 'Integrated Circuit With A Trench Capacitor Structure And Method Of Manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/383670
[patent_app_country] => US
[patent_app_date] => 2006-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3409
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20070267670.pdf
[firstpage_image] =>[orig_patent_app_number] => 11383670
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/383670 | Integrated circuit with a trench capacitor structure and method of manufacture | May 15, 2006 | Issued |
Array
(
[id] => 5043804
[patent_doc_number] => 20070262475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'POLYSILICON HARD MASK FOR ENHANCED ALIGNMENT SIGNAL'
[patent_app_type] => utility
[patent_app_number] => 11/382540
[patent_app_country] => US
[patent_app_date] => 2006-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2800
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20070262475.pdf
[firstpage_image] =>[orig_patent_app_number] => 11382540
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/382540 | Polysilicon hard mask for enhanced alignment signal | May 9, 2006 | Issued |
Array
(
[id] => 570305
[patent_doc_number] => 07465970
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-16
[patent_title] => 'Common pass gate layout of a D flip flop'
[patent_app_type] => utility
[patent_app_number] => 11/382700
[patent_app_country] => US
[patent_app_date] => 2006-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2069
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/465/07465970.pdf
[firstpage_image] =>[orig_patent_app_number] => 11382700
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/382700 | Common pass gate layout of a D flip flop | May 9, 2006 | Issued |
Array
(
[id] => 5014041
[patent_doc_number] => 20070257249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-08
[patent_title] => 'SILICON/SILCION GERMANINUM/SILICON BODY DEVICE WITH EMBEDDED CARBON DOPANT'
[patent_app_type] => utility
[patent_app_number] => 11/381810
[patent_app_country] => US
[patent_app_date] => 2006-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3321
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20070257249.pdf
[firstpage_image] =>[orig_patent_app_number] => 11381810
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/381810 | Silicon/silcion germaninum/silicon body device with embedded carbon dopant | May 4, 2006 | Issued |
Array
(
[id] => 289325
[patent_doc_number] => 07547941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-16
[patent_title] => 'NAND non-volatile two-bit memory and fabrication method'
[patent_app_type] => utility
[patent_app_number] => 11/417602
[patent_app_country] => US
[patent_app_date] => 2006-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 4155
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/547/07547941.pdf
[firstpage_image] =>[orig_patent_app_number] => 11417602
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/417602 | NAND non-volatile two-bit memory and fabrication method | May 3, 2006 | Issued |
Array
(
[id] => 7594599
[patent_doc_number] => 07626864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-01
[patent_title] => 'Electrically alterable non-volatile memory cells and arrays'
[patent_app_type] => utility
[patent_app_number] => 11/380418
[patent_app_country] => US
[patent_app_date] => 2006-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 11868
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/626/07626864.pdf
[firstpage_image] =>[orig_patent_app_number] => 11380418
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/380418 | Electrically alterable non-volatile memory cells and arrays | Apr 25, 2006 | Issued |
Array
(
[id] => 807009
[patent_doc_number] => 07420147
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-02
[patent_title] => 'Microchannel plate and method of manufacturing microchannel plate'
[patent_app_type] => utility
[patent_app_number] => 11/410324
[patent_app_country] => US
[patent_app_date] => 2006-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 67
[patent_figures_cnt] => 147
[patent_no_of_words] => 30866
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/420/07420147.pdf
[firstpage_image] =>[orig_patent_app_number] => 11410324
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/410324 | Microchannel plate and method of manufacturing microchannel plate | Apr 23, 2006 | Issued |
Array
(
[id] => 5677933
[patent_doc_number] => 20060183289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-17
[patent_title] => 'Back gate FinFET SRAM'
[patent_app_type] => utility
[patent_app_number] => 11/401786
[patent_app_country] => US
[patent_app_date] => 2006-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2236
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20060183289.pdf
[firstpage_image] =>[orig_patent_app_number] => 11401786
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/401786 | Back gate FinFET SRAM | Apr 10, 2006 | Issued |
Array
(
[id] => 5123543
[patent_doc_number] => 20070235813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-11
[patent_title] => 'Electronic device and a process for forming the electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/400945
[patent_app_country] => US
[patent_app_date] => 2006-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5686
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20070235813.pdf
[firstpage_image] =>[orig_patent_app_number] => 11400945
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/400945 | Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layer | Apr 9, 2006 | Issued |
Array
(
[id] => 5616193
[patent_doc_number] => 20060185725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'Method of forming multijuction solar cell structure with high band gap heterojunction middle cell'
[patent_app_type] => utility
[patent_app_number] => 11/401720
[patent_app_country] => US
[patent_app_date] => 2006-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4352
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20060185725.pdf
[firstpage_image] =>[orig_patent_app_number] => 11401720
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/401720 | Method of forming a multijunction solar cell structure with a GaAs/AIGaAs tunnel diode | Apr 9, 2006 | Issued |
Array
(
[id] => 345412
[patent_doc_number] => 07498602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets'
[patent_app_type] => utility
[patent_app_number] => 11/278910
[patent_app_country] => US
[patent_app_date] => 2006-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2619
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/498/07498602.pdf
[firstpage_image] =>[orig_patent_app_number] => 11278910
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/278910 | Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets | Apr 5, 2006 | Issued |
Array
(
[id] => 574287
[patent_doc_number] => 07462929
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-09
[patent_title] => 'Semiconductor device and an image sensing device'
[patent_app_type] => utility
[patent_app_number] => 11/392730
[patent_app_country] => US
[patent_app_date] => 2006-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 6339
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/462/07462929.pdf
[firstpage_image] =>[orig_patent_app_number] => 11392730
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/392730 | Semiconductor device and an image sensing device | Mar 29, 2006 | Issued |
Array
(
[id] => 370745
[patent_doc_number] => 07477520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Memory module'
[patent_app_type] => utility
[patent_app_number] => 11/391450
[patent_app_country] => US
[patent_app_date] => 2006-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 4368
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/477/07477520.pdf
[firstpage_image] =>[orig_patent_app_number] => 11391450
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/391450 | Memory module | Mar 28, 2006 | Issued |
Array
(
[id] => 5919323
[patent_doc_number] => 20060238961
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-26
[patent_title] => 'Circuit device'
[patent_app_type] => utility
[patent_app_number] => 11/391680
[patent_app_country] => US
[patent_app_date] => 2006-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6700
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20060238961.pdf
[firstpage_image] =>[orig_patent_app_number] => 11391680
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/391680 | Circuit device | Mar 28, 2006 | Issued |
Array
(
[id] => 253017
[patent_doc_number] => 07579651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-25
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/393530
[patent_app_country] => US
[patent_app_date] => 2006-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5204
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/579/07579651.pdf
[firstpage_image] =>[orig_patent_app_number] => 11393530
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/393530 | Semiconductor device | Mar 28, 2006 | Issued |
Array
(
[id] => 5125969
[patent_doc_number] => 20070238240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-11
[patent_title] => 'Method of forming a transistor in a non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 11/392240
[patent_app_country] => US
[patent_app_date] => 2006-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2940
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20070238240.pdf
[firstpage_image] =>[orig_patent_app_number] => 11392240
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/392240 | Method of forming a transistor in a non-volatile memory device | Mar 28, 2006 | Abandoned |
Array
(
[id] => 292673
[patent_doc_number] => 07544967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-09
[patent_title] => 'Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications'
[patent_app_type] => utility
[patent_app_number] => 11/391120
[patent_app_country] => US
[patent_app_date] => 2006-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2422
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/544/07544967.pdf
[firstpage_image] =>[orig_patent_app_number] => 11391120
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/391120 | Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications | Mar 27, 2006 | Issued |
Array
(
[id] => 573819
[patent_doc_number] => 07459389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-02
[patent_title] => 'Method of forming a semiconductor device having air gaps and the structure so formed'
[patent_app_type] => utility
[patent_app_number] => 11/391050
[patent_app_country] => US
[patent_app_date] => 2006-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 3214
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 851
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/459/07459389.pdf
[firstpage_image] =>[orig_patent_app_number] => 11391050
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/391050 | Method of forming a semiconductor device having air gaps and the structure so formed | Mar 27, 2006 | Issued |
Array
(
[id] => 14384
[patent_doc_number] => 07808022
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-10-05
[patent_title] => 'Cross talk reduction'
[patent_app_type] => utility
[patent_app_number] => 11/392410
[patent_app_country] => US
[patent_app_date] => 2006-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3685
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/808/07808022.pdf
[firstpage_image] =>[orig_patent_app_number] => 11392410
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/392410 | Cross talk reduction | Mar 27, 2006 | Issued |
Array
(
[id] => 795873
[patent_doc_number] => 07429789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-30
[patent_title] => 'Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same'
[patent_app_type] => utility
[patent_app_number] => 11/390386
[patent_app_country] => US
[patent_app_date] => 2006-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11219
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/429/07429789.pdf
[firstpage_image] =>[orig_patent_app_number] => 11390386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/390386 | Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same | Mar 27, 2006 | Issued |