Search

Dariush Seif

Examiner (ID: 17097, Phone: (408)918-7542 , Office: P/3721 )

Most Active Art Unit
3731
Art Unit(s)
3721, 3731
Total Applications
663
Issued Applications
433
Pending Applications
83
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6306851 [patent_doc_number] => 20020094682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Method for fabricating a III-V nitride film and an apparatus for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/004345 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2894 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094682.pdf [firstpage_image] =>[orig_patent_app_number] => 10004345 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004345
Method for fabricating a III-V nitride film and an apparatus for fabricating the same Nov 1, 2001 Abandoned
Array ( [id] => 1239586 [patent_doc_number] => 06686233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Integration of high voltage self-aligned MOS components' [patent_app_type] => B2 [patent_app_number] => 09/985447 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4202 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 455 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686233.pdf [firstpage_image] =>[orig_patent_app_number] => 09985447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/985447
Integration of high voltage self-aligned MOS components Nov 1, 2001 Issued
Array ( [id] => 6081176 [patent_doc_number] => 20020081825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method for reproducibly forming a predetermined quantum dot structure and device produced using same' [patent_app_type] => new [patent_app_number] => 09/984116 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4249 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081825.pdf [firstpage_image] =>[orig_patent_app_number] => 09984116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984116
Method for reproducibly forming a predetermined quantum dot structure and device produced using same Oct 28, 2001 Abandoned
Array ( [id] => 7964329 [patent_doc_number] => 06680262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface' [patent_app_type] => B2 [patent_app_number] => 10/007756 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2650 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680262.pdf [firstpage_image] =>[orig_patent_app_number] => 10007756 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007756
Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface Oct 24, 2001 Issued
Array ( [id] => 6706431 [patent_doc_number] => 20030153165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method of forming silicon-based thin film, method of forming silicon-based semiconductor layer, and photovoltaic element' [patent_app_type] => new [patent_app_number] => 09/983427 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 23793 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153165.pdf [firstpage_image] =>[orig_patent_app_number] => 09983427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983427
Method of forming silicon-based thin film, method of forming silicon-based semiconductor layer, and photovoltaic element Oct 23, 2001 Issued
Array ( [id] => 6725245 [patent_doc_number] => 20030207557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => new [patent_app_number] => 09/983063 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 28377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207557.pdf [firstpage_image] =>[orig_patent_app_number] => 09983063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983063
Semiconductor device and its manufacturing method Oct 22, 2001 Abandoned
Array ( [id] => 6657328 [patent_doc_number] => 20030077917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method of fabricating a void-free barrier layer' [patent_app_type] => new [patent_app_number] => 09/982867 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1322 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077917.pdf [firstpage_image] =>[orig_patent_app_number] => 09982867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/982867
Method of fabricating a void-free barrier layer Oct 21, 2001 Abandoned
Array ( [id] => 5844583 [patent_doc_number] => 20020132454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Method of forming crystalline semiconductor thin film on base substrate, lamination formed with crystalline semiconductor thin film and color filter' [patent_app_type] => new [patent_app_number] => 09/977947 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20020132454.pdf [firstpage_image] =>[orig_patent_app_number] => 09977947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977947
Method of forming crystalline semiconductor thin film on base substrate, lamination formed with crystalline semiconductor thin film and color filter Oct 16, 2001 Issued
Array ( [id] => 6813754 [patent_doc_number] => 20030073304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Selective tungsten stud as copper diffusion barrier to silicon contact' [patent_app_type] => new [patent_app_number] => 09/981593 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3784 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073304.pdf [firstpage_image] =>[orig_patent_app_number] => 09981593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981593
Selective tungsten stud as copper diffusion barrier to silicon contact Oct 15, 2001 Abandoned
Array ( [id] => 1253388 [patent_doc_number] => 06670272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method for reducing dishing in chemical mechanical polishing' [patent_app_type] => B2 [patent_app_number] => 09/976117 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2647 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670272.pdf [firstpage_image] =>[orig_patent_app_number] => 09976117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976117
Method for reducing dishing in chemical mechanical polishing Oct 11, 2001 Issued
Array ( [id] => 6813740 [patent_doc_number] => 20030073290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method for growing ultra thin nitrided oxide' [patent_app_type] => new [patent_app_number] => 09/975256 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2741 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073290.pdf [firstpage_image] =>[orig_patent_app_number] => 09975256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975256
Method for growing ultra thin nitrided oxide Oct 11, 2001 Issued
Array ( [id] => 6811760 [patent_doc_number] => 20030071310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method to increase substrate potential in MOS transistors used in ESD protection circuits' [patent_app_type] => new [patent_app_number] => 09/975107 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6028 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20030071310.pdf [firstpage_image] =>[orig_patent_app_number] => 09975107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975107
Method to increase substrate potential in MOS transistors used in ESD protection circuits Oct 10, 2001 Abandoned
Array ( [id] => 1361017 [patent_doc_number] => 06577020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'High contrast alignment marks having flexible placement' [patent_app_type] => B2 [patent_app_number] => 09/976878 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2572 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/577/06577020.pdf [firstpage_image] =>[orig_patent_app_number] => 09976878 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976878
High contrast alignment marks having flexible placement Oct 10, 2001 Issued
09/974917 Method for forming SAC using a dielectric as a BARC and FICD enlarger Oct 9, 2001 Abandoned
Array ( [id] => 6405986 [patent_doc_number] => 20020037636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Method for producing an edge termination suitable for high voltages in a basic material wafer prefabricated according to the principle of lateral charge compensation' [patent_app_type] => new [patent_app_number] => 09/974937 [patent_app_country] => US [patent_app_date] => 2001-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2790 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037636.pdf [firstpage_image] =>[orig_patent_app_number] => 09974937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974937
Method for producing an edge termination suitable for high voltages in a basic material wafer prefabricated according to the principle of lateral charge compensation Oct 9, 2001 Issued
Array ( [id] => 6452892 [patent_doc_number] => 20020129323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Connection device and test system' [patent_app_type] => new [patent_app_number] => 09/971606 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16878 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129323.pdf [firstpage_image] =>[orig_patent_app_number] => 09971606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971606
Connection device and test system Oct 8, 2001 Issued
Array ( [id] => 1270168 [patent_doc_number] => 06653199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method of forming inside rough and outside smooth HSG electrodes and capacitor structure' [patent_app_type] => B2 [patent_app_number] => 09/973505 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2961 [patent_no_of_claims] => 121 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653199.pdf [firstpage_image] =>[orig_patent_app_number] => 09973505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973505
Method of forming inside rough and outside smooth HSG electrodes and capacitor structure Oct 8, 2001 Issued
Array ( [id] => 6811740 [patent_doc_number] => 20030071290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication' [patent_app_type] => new [patent_app_number] => 09/974167 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3675 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20030071290.pdf [firstpage_image] =>[orig_patent_app_number] => 09974167 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974167
Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication Oct 8, 2001 Issued
Array ( [id] => 6081223 [patent_doc_number] => 20020081843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Semicoductor device and method of manufacturing of the same' [patent_app_type] => new [patent_app_number] => 09/971268 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6540 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081843.pdf [firstpage_image] =>[orig_patent_app_number] => 09971268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971268
Semiconductor device and method of manufacturing of the same Oct 4, 2001 Issued
Array ( [id] => 1414501 [patent_doc_number] => 06521512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method for fabricating a thin, free-standing semiconductor device layer and for making a three-dimensionally integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/970977 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4063 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521512.pdf [firstpage_image] =>[orig_patent_app_number] => 09970977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/970977
Method for fabricating a thin, free-standing semiconductor device layer and for making a three-dimensionally integrated circuit Oct 3, 2001 Issued
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