Darlene M. Ritchie

Array ( [id] => 14843365 [patent_doc_number] => 20190280083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY [patent_app_type] => utility [patent_app_number] => 16/413447 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16098625 [patent_doc_number] => 20200203299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => CHIP PACKAGE STRUCTURE WITH DUMMY BUMP AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/405429 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16440579 [patent_doc_number] => 20200357906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => III-V DEPLETION MODE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/405457 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17032910 [patent_doc_number] => 11094728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Image pickup device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/391040 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10426 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16226371 [patent_doc_number] => 20200251488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/388054 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16835457 [patent_doc_number] => 11011719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Electroluminescence device, lighting panel, and vehicle lamp group [patent_app_type] => utility [patent_app_number] => 16/385260 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8644 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15388877 [patent_doc_number] => 10535637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Methods to form reduced form factor radio frequency system-in-package [patent_app_type] => utility [patent_app_number] => 16/377477 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 13301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16377477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676697 [patent_doc_number] => 20190237463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => FIN-FET DEVICES [patent_app_type] => utility [patent_app_number] => 16/376278 [patent_app_country] => US [patent_app_date] => 2019-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16376278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15807471 [patent_doc_number] => 20200126878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/374762 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16448546 [patent_doc_number] => 10840478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Display panel [patent_app_type] => utility [patent_app_number] => 16/374040 [patent_app_country] => US [patent_app_date] => 2019-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 12303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14631285 [patent_doc_number] => 20190229012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => Interlayer Dielectric Film in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 16/371847 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14889351 [patent_doc_number] => 10424727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Spin transfer torque cell for magnetic random access memory [patent_app_type] => utility [patent_app_number] => 16/364794 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14573463 [patent_doc_number] => 20190214339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => REDUCTION OF STRESS IN VIA STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/352946 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14542529 [patent_doc_number] => 20190206886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/298247 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16148103 [patent_doc_number] => 10707128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains [patent_app_type] => utility [patent_app_number] => 16/287578 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 9690 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14509477 [patent_doc_number] => 20190198393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => FABRICATION OF SELF-ALIGNED GATE CONTACTS AND SOURCE/DRAIN CONTACTS DIRECTLY ABOVE GATE ELECTRODES AND SOURCE/DRAINS [patent_app_type] => utility [patent_app_number] => 16/286055 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16268633 [patent_doc_number] => 20200270120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => Full Symmetric Multi-Throw Switch Using Conformal Pinched Through Via [patent_app_type] => utility [patent_app_number] => 16/283306 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14446923 [patent_doc_number] => 20190181335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => PHASE CHANGEABLE MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/274796 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16274796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14920471 [patent_doc_number] => 10431562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-01 [patent_title] => Back side metallization [patent_app_type] => utility [patent_app_number] => 16/260794 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6349 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16707750 [patent_doc_number] => 10957694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation [patent_app_type] => utility [patent_app_number] => 16/256143 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256143 [rel_patent_id] =>[rel_patent_doc_number] =>)