
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14587755
[patent_doc_number] => 20190221486
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => INSPECTION SYSTEM AND INSPECTION METHOD
[patent_app_type] => utility
[patent_app_number] => 16/360424
[patent_app_country] => US
[patent_app_date] => 2019-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10152
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360424
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/360424 | Inspection system and inspection method | Mar 20, 2019 | Issued |
Array
(
[id] => 14955087
[patent_doc_number] => 10438822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-08
[patent_title] => Method for prefixing of substrates
[patent_app_type] => utility
[patent_app_number] => 16/294235
[patent_app_country] => US
[patent_app_date] => 2019-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 14969
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294235
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/294235 | Method for prefixing of substrates | Mar 5, 2019 | Issued |
Array
(
[id] => 14542727
[patent_doc_number] => 20190206985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/294190
[patent_app_country] => US
[patent_app_date] => 2019-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7364
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 458
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294190
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/294190 | Method of manufacturing semiconductor device | Mar 5, 2019 | Issued |
Array
(
[id] => 17310122
[patent_doc_number] => 11211248
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-28
[patent_title] => SiC electronic device fabricated by Al/Be co-implantation
[patent_app_type] => utility
[patent_app_number] => 16/976667
[patent_app_country] => US
[patent_app_date] => 2019-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4922
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16976667
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/976667 | SiC electronic device fabricated by Al/Be co-implantation | Feb 27, 2019 | Issued |
Array
(
[id] => 16264639
[patent_doc_number] => 10756086
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-08-25
[patent_title] => Method for manufacturing semiconductor and structure and operation of the same
[patent_app_type] => utility
[patent_app_number] => 16/281950
[patent_app_country] => US
[patent_app_date] => 2019-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5757
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281950
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/281950 | Method for manufacturing semiconductor and structure and operation of the same | Feb 20, 2019 | Issued |
Array
(
[id] => 16715929
[patent_doc_number] => 20210083076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => FABRICATION OF ELECTRONIC DEVICES USING SACRIFICIAL SEED LAYERS
[patent_app_type] => utility
[patent_app_number] => 16/968294
[patent_app_country] => US
[patent_app_date] => 2019-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2179
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16968294
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/968294 | Fabrication of electronic devices using sacrificial seed layers | Feb 20, 2019 | Issued |
Array
(
[id] => 15315881
[patent_doc_number] => 10522658
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-12-31
[patent_title] => Vertical field effect transistor having improved uniformity
[patent_app_type] => utility
[patent_app_number] => 16/280326
[patent_app_country] => US
[patent_app_date] => 2019-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 35
[patent_no_of_words] => 7398
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280326
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/280326 | Vertical field effect transistor having improved uniformity | Feb 19, 2019 | Issued |
Array
(
[id] => 14476073
[patent_doc_number] => 20190189685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-20
[patent_title] => METHOD OF MASKLESS PARALLEL PICK-AND-PLACE TRANSFER OF MICRO-DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/270235
[patent_app_country] => US
[patent_app_date] => 2019-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7491
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270235
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/270235 | Method of maskless parallel pick-and-place transfer of micro-devices | Feb 6, 2019 | Issued |
Array
(
[id] => 16241508
[patent_doc_number] => 20200258742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => METHODS AND APPARATUSES RELATED TO SHAPING WAFERS FABRICATED BY ION IMPLANTATION
[patent_app_type] => utility
[patent_app_number] => 16/269837
[patent_app_country] => US
[patent_app_date] => 2019-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269837
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/269837 | Methods and apparatuses related to shaping wafers fabricated by ion implantation | Feb 6, 2019 | Issued |
Array
(
[id] => 14382507
[patent_doc_number] => 20190165166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/263643
[patent_app_country] => US
[patent_app_date] => 2019-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8963
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 503
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263643
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/263643 | Method of manufacturing semiconductor device | Jan 30, 2019 | Issued |
Array
(
[id] => 14631467
[patent_doc_number] => 20190229103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/257722
[patent_app_country] => US
[patent_app_date] => 2019-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8447
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257722
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/257722 | SEMICONDUCTOR DEVICE | Jan 24, 2019 | Abandoned |
Array
(
[id] => 18967481
[patent_doc_number] => 11901262
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Cooling solution including microchannel arrays and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/256831
[patent_app_country] => US
[patent_app_date] => 2019-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 9488
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256831
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/256831 | Cooling solution including microchannel arrays and methods of forming the same | Jan 23, 2019 | Issued |
Array
(
[id] => 17239542
[patent_doc_number] => 11183433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Method of evaluating silicon layer and a method of manufacturing silicon epitaxial wafer
[patent_app_type] => utility
[patent_app_number] => 16/962961
[patent_app_country] => US
[patent_app_date] => 2019-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7718
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962961
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/962961 | Method of evaluating silicon layer and a method of manufacturing silicon epitaxial wafer | Jan 17, 2019 | Issued |
Array
(
[id] => 14317381
[patent_doc_number] => 20190148394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/243319
[patent_app_country] => US
[patent_app_date] => 2019-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18186
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 411
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243319
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/243319 | Semiconductor device and method of manufacturing the same | Jan 8, 2019 | Issued |
Array
(
[id] => 17470333
[patent_doc_number] => 11276816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-15
[patent_title] => Method of manufacturing magnetic tunnel junction and magnetic tunnel junction
[patent_app_type] => utility
[patent_app_number] => 16/489838
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 28
[patent_no_of_words] => 11025
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16489838
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/489838 | Method of manufacturing magnetic tunnel junction and magnetic tunnel junction | Jan 6, 2019 | Issued |
Array
(
[id] => 14738241
[patent_doc_number] => 10388530
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-20
[patent_title] => Method of manufacturing semiconductor device and substrate processing apparatus
[patent_app_type] => utility
[patent_app_number] => 16/240197
[patent_app_country] => US
[patent_app_date] => 2019-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 23355
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240197
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/240197 | Method of manufacturing semiconductor device and substrate processing apparatus | Jan 3, 2019 | Issued |
Array
(
[id] => 17818507
[patent_doc_number] => 11424129
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-23
[patent_title] => Method of etching boron-doped p-type silicon wafer, method of evaluating metal contamination of boron-doped p-type silicon wafer and method of manufacturing boron-doped p-type silicon wafer
[patent_app_type] => utility
[patent_app_number] => 16/982233
[patent_app_country] => US
[patent_app_date] => 2018-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7055
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16982233
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/982233 | Method of etching boron-doped p-type silicon wafer, method of evaluating metal contamination of boron-doped p-type silicon wafer and method of manufacturing boron-doped p-type silicon wafer | Dec 11, 2018 | Issued |
Array
(
[id] => 16067871
[patent_doc_number] => 10692900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-06-23
[patent_title] => Method of manufacturing array substrate and display panel
[patent_app_type] => utility
[patent_app_number] => 16/315599
[patent_app_country] => US
[patent_app_date] => 2018-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4144
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16315599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/315599 | Method of manufacturing array substrate and display panel | Dec 6, 2018 | Issued |
Array
(
[id] => 19081119
[patent_doc_number] => 11950515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-02
[patent_title] => Electrical contacts for low dimensional materials
[patent_app_type] => utility
[patent_app_number] => 17/044504
[patent_app_country] => US
[patent_app_date] => 2018-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 4655
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17044504
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/044504 | Electrical contacts for low dimensional materials | Dec 5, 2018 | Issued |
Array
(
[id] => 17129212
[patent_doc_number] => 20210303981
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => RESERVOIR ELEMENT AND NEUROMORPHIC ELEMENT
[patent_app_type] => utility
[patent_app_number] => 17/265622
[patent_app_country] => US
[patent_app_date] => 2018-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9718
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17265622
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/265622 | Reservoir element and neuromorphic element | Nov 20, 2018 | Issued |