Darlington Ly

Array ( [id] => 15760557 [patent_doc_number] => 10622408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Resistive memory cell structures and methods [patent_app_type] => utility [patent_app_number] => 16/022945 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 5899 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13499655 [patent_doc_number] => 20180301370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-on-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods and Integrated Circuitry [patent_app_type] => utility [patent_app_number] => 16/017874 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16433064 [patent_doc_number] => 10833163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Epitaxial structure of N-face group III nitride, active device, and method for fabricating the same with integration and polarity inversion [patent_app_type] => utility [patent_app_number] => 16/000057 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 51 [patent_no_of_words] => 8552 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14317687 [patent_doc_number] => 20190148547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/997793 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16432889 [patent_doc_number] => 10832986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Fan-out semiconductor package [patent_app_type] => utility [patent_app_number] => 16/000094 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 8379 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14125767 [patent_doc_number] => 10249749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/997856 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 9387 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17559321 [patent_doc_number] => 11316044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods [patent_app_type] => utility [patent_app_number] => 15/997997 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 11122 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16132441 [patent_doc_number] => 10699988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Chip packaging method and package structure [patent_app_type] => utility [patent_app_number] => 15/997846 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2863 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15109115 [patent_doc_number] => 10475889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Gallium nitride power amplifier integration with metal-oxide-semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/997991 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15218099 [patent_doc_number] => 20190371736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => INTERCONNECT STRUCTURES WITH REDUCED CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/000174 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17166391 [patent_doc_number] => 11152504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Methods of fabricating field-effect transistors [patent_app_type] => utility [patent_app_number] => 15/997866 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 13998 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14079679 [patent_doc_number] => 20190088727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/000050 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14110997 [patent_doc_number] => 20190097174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PACKAGE STRUCTURE OF DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/000148 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14110765 [patent_doc_number] => 20190097058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => OXIDE THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/995706 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14785337 [patent_doc_number] => 20190267566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => DISPLAY COMPONENT PACKAGING STRUCTURE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/320214 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16320214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17032782 [patent_doc_number] => 11094600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Method of predicting warpage of silicon wafer and method of producing silicon wafer [patent_app_type] => utility [patent_app_number] => 16/970063 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5366 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16970063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15077935 [patent_doc_number] => 10468468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Organic light emitting diode display device and organic light emitting diode thereof [patent_app_type] => utility [patent_app_number] => 15/969504 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7156 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13950875 [patent_doc_number] => 10211216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/961334 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 67 [patent_no_of_words] => 18170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15961334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13392553 [patent_doc_number] => 20180247819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 15/961277 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15961277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13528783 [patent_doc_number] => 20180315934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => COMPOSITION CONTAINING NAPHTHALOCYANINE DERIVATIVE, PHOTOELECTRIC CONVERSION ELEMENT CONTAINING THE SAME, AND IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 15/959097 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959097 [rel_patent_id] =>[rel_patent_doc_number] =>)