
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12144934
[patent_doc_number] => 09879176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-30
[patent_title] => 'Organic electroluminescent element, production method for the same, planar light source, lighting device, and display device'
[patent_app_type] => utility
[patent_app_number] => 12/864193
[patent_app_country] => US
[patent_app_date] => 2009-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 9759
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12864193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/864193 | Organic electroluminescent element, production method for the same, planar light source, lighting device, and display device | Jan 20, 2009 | Issued |
Array
(
[id] => 5514903
[patent_doc_number] => 20090215210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'METHOD OF MANUFACTURING LIGHT EMITTING DIODE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/351668
[patent_app_country] => US
[patent_app_date] => 2009-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3907
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20090215210.pdf
[firstpage_image] =>[orig_patent_app_number] => 12351668
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/351668 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE DEVICE | Jan 8, 2009 | Abandoned |
Array
(
[id] => 74187
[patent_doc_number] => 07749913
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-06
[patent_title] => 'Semiconductor device manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 12/336348
[patent_app_country] => US
[patent_app_date] => 2008-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 26
[patent_no_of_words] => 5197
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/749/07749913.pdf
[firstpage_image] =>[orig_patent_app_number] => 12336348
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/336348 | Semiconductor device manufacturing method | Dec 15, 2008 | Issued |
Array
(
[id] => 4599428
[patent_doc_number] => 07977177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-12
[patent_title] => 'Methods of forming nano-devices using nanostructures having self-assembly characteristics'
[patent_app_type] => utility
[patent_app_number] => 12/330898
[patent_app_country] => US
[patent_app_date] => 2008-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 3613
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/977/07977177.pdf
[firstpage_image] =>[orig_patent_app_number] => 12330898
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/330898 | Methods of forming nano-devices using nanostructures having self-assembly characteristics | Dec 8, 2008 | Issued |
Array
(
[id] => 5428652
[patent_doc_number] => 20090087962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY'
[patent_app_type] => utility
[patent_app_number] => 12/325694
[patent_app_country] => US
[patent_app_date] => 2008-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7311
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20090087962.pdf
[firstpage_image] =>[orig_patent_app_number] => 12325694
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/325694 | Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby | Nov 30, 2008 | Issued |
Array
(
[id] => 7762094
[patent_doc_number] => 08114731
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor'
[patent_app_type] => utility
[patent_app_number] => 12/276507
[patent_app_country] => US
[patent_app_date] => 2008-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5685
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/114/08114731.pdf
[firstpage_image] =>[orig_patent_app_number] => 12276507
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/276507 | Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor | Nov 23, 2008 | Issued |
Array
(
[id] => 64915
[patent_doc_number] => 07759720
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-20
[patent_title] => 'Non-volatile semiconductor memory device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/273308
[patent_app_country] => US
[patent_app_date] => 2008-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 48
[patent_no_of_words] => 12686
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/759/07759720.pdf
[firstpage_image] =>[orig_patent_app_number] => 12273308
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/273308 | Non-volatile semiconductor memory device and method of manufacturing the same | Nov 17, 2008 | Issued |
Array
(
[id] => 7540290
[patent_doc_number] => 08058133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-15
[patent_title] => 'Method of fabrication of metal oxide semiconductor field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 12/273517
[patent_app_country] => US
[patent_app_date] => 2008-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 7527
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/058/08058133.pdf
[firstpage_image] =>[orig_patent_app_number] => 12273517
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/273517 | Method of fabrication of metal oxide semiconductor field effect transistor | Nov 17, 2008 | Issued |
Array
(
[id] => 8807700
[patent_doc_number] => 08445352
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-21
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/268538
[patent_app_country] => US
[patent_app_date] => 2008-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 55
[patent_no_of_words] => 13868
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12268538
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/268538 | Manufacturing method of semiconductor device | Nov 10, 2008 | Issued |
Array
(
[id] => 5419787
[patent_doc_number] => 20090146241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/268028
[patent_app_country] => US
[patent_app_date] => 2008-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2862
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20090146241.pdf
[firstpage_image] =>[orig_patent_app_number] => 12268028
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/268028 | Semiconductor apparatus and manufacturing method thereof | Nov 9, 2008 | Issued |
Array
(
[id] => 7550627
[patent_doc_number] => 08062959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Method of manufacturing semiconductor element'
[patent_app_type] => utility
[patent_app_number] => 12/289767
[patent_app_country] => US
[patent_app_date] => 2008-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 15568
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/062/08062959.pdf
[firstpage_image] =>[orig_patent_app_number] => 12289767
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/289767 | Method of manufacturing semiconductor element | Nov 2, 2008 | Issued |
| 12/290188 | QFN process for strip test | Oct 26, 2008 | Abandoned |
Array
(
[id] => 7545339
[patent_doc_number] => 08053310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-08
[patent_title] => 'Method for defect reduction for memory cell capacitors'
[patent_app_type] => utility
[patent_app_number] => 12/259138
[patent_app_country] => US
[patent_app_date] => 2008-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 4455
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/053/08053310.pdf
[firstpage_image] =>[orig_patent_app_number] => 12259138
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/259138 | Method for defect reduction for memory cell capacitors | Oct 26, 2008 | Issued |
Array
(
[id] => 7518815
[patent_doc_number] => 07972916
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-07-05
[patent_title] => 'Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses'
[patent_app_type] => utility
[patent_app_number] => 12/256357
[patent_app_country] => US
[patent_app_date] => 2008-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6749
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/972/07972916.pdf
[firstpage_image] =>[orig_patent_app_number] => 12256357
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/256357 | Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses | Oct 21, 2008 | Issued |
Array
(
[id] => 83541
[patent_doc_number] => 07741213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-22
[patent_title] => 'Semiconductor device, DRAM integrated circuit device, and method of producing the same'
[patent_app_type] => utility
[patent_app_number] => 12/285848
[patent_app_country] => US
[patent_app_date] => 2008-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 87
[patent_no_of_words] => 19337
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/741/07741213.pdf
[firstpage_image] =>[orig_patent_app_number] => 12285848
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/285848 | Semiconductor device, DRAM integrated circuit device, and method of producing the same | Oct 14, 2008 | Issued |
Array
(
[id] => 5281408
[patent_doc_number] => 20090095081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/285825
[patent_app_country] => US
[patent_app_date] => 2008-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 9421
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20090095081.pdf
[firstpage_image] =>[orig_patent_app_number] => 12285825
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/285825 | Semiconductor device | Oct 14, 2008 | Abandoned |
Array
(
[id] => 185017
[patent_doc_number] => 07648908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-19
[patent_title] => 'Method for forming inlaid interconnect'
[patent_app_type] => utility
[patent_app_number] => 12/247507
[patent_app_country] => US
[patent_app_date] => 2008-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 4240
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/648/07648908.pdf
[firstpage_image] =>[orig_patent_app_number] => 12247507
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/247507 | Method for forming inlaid interconnect | Oct 7, 2008 | Issued |
Array
(
[id] => 4619104
[patent_doc_number] => 07998822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-16
[patent_title] => 'Semiconductor fabrication process including silicide stringer removal processing'
[patent_app_type] => utility
[patent_app_number] => 12/244413
[patent_app_country] => US
[patent_app_date] => 2008-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2815
[patent_no_of_claims] => 21
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/998/07998822.pdf
[firstpage_image] =>[orig_patent_app_number] => 12244413
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/244413 | Semiconductor fabrication process including silicide stringer removal processing | Oct 1, 2008 | Issued |
Array
(
[id] => 190836
[patent_doc_number] => 07642147
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-01-05
[patent_title] => 'Methods for removing sidewall spacers'
[patent_app_type] => utility
[patent_app_number] => 12/242977
[patent_app_country] => US
[patent_app_date] => 2008-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3612
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/642/07642147.pdf
[firstpage_image] =>[orig_patent_app_number] => 12242977
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/242977 | Methods for removing sidewall spacers | Sep 30, 2008 | Issued |
Array
(
[id] => 5285060
[patent_doc_number] => 20090098735
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'METHOD OF FORMING ISOLATION LAYER IN SEMICONDCUTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/241127
[patent_app_country] => US
[patent_app_date] => 2008-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1688
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20090098735.pdf
[firstpage_image] =>[orig_patent_app_number] => 12241127
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/241127 | METHOD OF FORMING ISOLATION LAYER IN SEMICONDCUTOR DEVICE | Sep 29, 2008 | Abandoned |