Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5428663 [patent_doc_number] => 20090087973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'RETENTION IMPROVEMENT IN DUAL-GATE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/240848 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2093 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20090087973.pdf [firstpage_image] =>[orig_patent_app_number] => 12240848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240848
RETENTION IMPROVEMENT IN DUAL-GATE MEMORY Sep 28, 2008 Abandoned
Array ( [id] => 6372071 [patent_doc_number] => 20100075460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking' [patent_app_type] => utility [patent_app_number] => 12/236967 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2727 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20100075460.pdf [firstpage_image] =>[orig_patent_app_number] => 12236967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236967
Low cost die-to-wafer alignment/bond for 3d IC stacking Sep 23, 2008 Issued
Array ( [id] => 6349077 [patent_doc_number] => 20100071930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'SOLVENT SOFTENING TO ALLOW DIE PLACEMENT' [patent_app_type] => utility [patent_app_number] => 12/236848 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3964 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20100071930.pdf [firstpage_image] =>[orig_patent_app_number] => 12236848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236848
Solvent softening to allow die placement Sep 23, 2008 Issued
Array ( [id] => 6372203 [patent_doc_number] => 20100075485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'INTEGRATED EMITTER FORMATION AND PASSIVATION' [patent_app_type] => utility [patent_app_number] => 12/234848 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20100075485.pdf [firstpage_image] =>[orig_patent_app_number] => 12234848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234848
Integrated emitter formation and passivation Sep 21, 2008 Issued
Array ( [id] => 204647 [patent_doc_number] => 07629271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-08 [patent_title] => 'High stress diamond like carbon film' [patent_app_type] => utility [patent_app_number] => 12/233881 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629271.pdf [firstpage_image] =>[orig_patent_app_number] => 12233881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233881
High stress diamond like carbon film Sep 18, 2008 Issued
Array ( [id] => 5465131 [patent_doc_number] => 20090325331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'METHOD FOR MANUFACTURING PIXEL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/233607 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3382 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12233607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233607
Method for manufacturing pixel structure Sep 18, 2008 Issued
Array ( [id] => 5296663 [patent_doc_number] => 20090011589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'METHOD OF MANUFACTURING SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/212317 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3965 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20090011589.pdf [firstpage_image] =>[orig_patent_app_number] => 12212317 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212317
METHOD OF MANUFACTURING SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE Sep 16, 2008 Abandoned
Array ( [id] => 6304821 [patent_doc_number] => 20100068832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'METHOD FOR THE PROTECTION OF INFORMATION IN MULTI-PROJECT WAFERS' [patent_app_type] => utility [patent_app_number] => 12/211071 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3522 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20100068832.pdf [firstpage_image] =>[orig_patent_app_number] => 12211071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211071
METHOD FOR THE PROTECTION OF INFORMATION IN MULTI-PROJECT WAFERS Sep 14, 2008 Abandoned
Array ( [id] => 5296639 [patent_doc_number] => 20090011565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Field effect transistor structure with abrupt source/drain junctions' [patent_app_type] => utility [patent_app_number] => 12/231172 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20090011565.pdf [firstpage_image] =>[orig_patent_app_number] => 12231172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/231172
Field effect transistor structure with abrupt source/drain junctions Aug 27, 2008 Issued
Array ( [id] => 6177383 [patent_doc_number] => 20110121267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'ORGANIC ELECTROLUMINESCENCE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/675101 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10344 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121267.pdf [firstpage_image] =>[orig_patent_app_number] => 12675101 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/675101
Organic electroluminescence device Aug 27, 2008 Issued
Array ( [id] => 6137259 [patent_doc_number] => 20110127552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'LIGHT OUTPUT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/674940 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20110127552.pdf [firstpage_image] =>[orig_patent_app_number] => 12674940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/674940
Light output device Aug 27, 2008 Issued
Array ( [id] => 92066 [patent_doc_number] => 07737027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/229808 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737027.pdf [firstpage_image] =>[orig_patent_app_number] => 12229808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/229808
Method of manufacturing a semiconductor device Aug 26, 2008 Issued
Array ( [id] => 6587850 [patent_doc_number] => 20100048025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'NANOSTRUCTURES AND NANOSTRUCTURE FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/197997 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3248 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20100048025.pdf [firstpage_image] =>[orig_patent_app_number] => 12197997 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/197997
NANOSTRUCTURES AND NANOSTRUCTURE FABRICATION Aug 24, 2008 Abandoned
Array ( [id] => 6538175 [patent_doc_number] => 20100044225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'NANO-STRUCTURE WITH CAPS' [patent_app_type] => utility [patent_app_number] => 12/197765 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3840 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044225.pdf [firstpage_image] =>[orig_patent_app_number] => 12197765 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/197765
NANO-STRUCTURE WITH CAPS Aug 24, 2008 Abandoned
Array ( [id] => 8469736 [patent_doc_number] => 08298914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => '3D integrated circuit device fabrication using interface wafer as permanent carrier' [patent_app_type] => utility [patent_app_number] => 12/194198 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5823 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12194198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/194198
3D integrated circuit device fabrication using interface wafer as permanent carrier Aug 18, 2008 Issued
Array ( [id] => 8281807 [patent_doc_number] => 08215910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Aircraft turbomachine fan comprising a balancing flange concealed by the inlet cone' [patent_app_type] => utility [patent_app_number] => 12/193886 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2705 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12193886 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193886
Aircraft turbomachine fan comprising a balancing flange concealed by the inlet cone Aug 18, 2008 Issued
Array ( [id] => 5327846 [patent_doc_number] => 20090108323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Method of forming nonvolatile memory device having floating gate and related device' [patent_app_type] => utility [patent_app_number] => 12/228772 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5986 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108323.pdf [firstpage_image] =>[orig_patent_app_number] => 12228772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/228772
Method of forming nonvolatile memory device having floating gate and related device Aug 14, 2008 Issued
Array ( [id] => 8421669 [patent_doc_number] => 08278157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Methods for fabricating array substrates' [patent_app_type] => utility [patent_app_number] => 12/190688 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 35 [patent_no_of_words] => 5250 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 464 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12190688 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190688
Methods for fabricating array substrates Aug 12, 2008 Issued
Array ( [id] => 4711205 [patent_doc_number] => 20080299731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE' [patent_app_type] => utility [patent_app_number] => 12/190657 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2235 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299731.pdf [firstpage_image] =>[orig_patent_app_number] => 12190657 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190657
ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE Aug 12, 2008 Abandoned
Array ( [id] => 5444209 [patent_doc_number] => 20090045435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Stamp having nanoscale structure and applications therefore in light-emitting device' [patent_app_type] => utility [patent_app_number] => 12/222548 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045435.pdf [firstpage_image] =>[orig_patent_app_number] => 12222548 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222548
Stamp having nanoscale structure and applications therefore in light-emitting device Aug 11, 2008 Issued
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