Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5760274 [patent_doc_number] => 20060211219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Substrate stiffness method and resulting devices for layer transfer process' [patent_app_type] => utility [patent_app_number] => 11/361855 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21075 [patent_no_of_claims] => 144 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211219.pdf [firstpage_image] =>[orig_patent_app_number] => 11361855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/361855
Substrate stiffness method and resulting devices for layer transfer process Feb 23, 2006 Issued
Array ( [id] => 277902 [patent_doc_number] => 07556976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation' [patent_app_type] => utility [patent_app_number] => 11/360756 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 17032 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/556/07556976.pdf [firstpage_image] =>[orig_patent_app_number] => 11360756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360756
Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation Feb 22, 2006 Issued
Array ( [id] => 5628769 [patent_doc_number] => 20060145237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Non-volatile memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/324415 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10363 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145237.pdf [firstpage_image] =>[orig_patent_app_number] => 11324415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324415
Non-volatile memory device and method of manufacturing the same Jan 2, 2006 Abandoned
Array ( [id] => 5593799 [patent_doc_number] => 20060157715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/314135 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20060157715.pdf [firstpage_image] =>[orig_patent_app_number] => 11314135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314135
Semiconductor device and method of manufacturing the same Dec 20, 2005 Issued
Array ( [id] => 907071 [patent_doc_number] => 07332400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance' [patent_app_type] => utility [patent_app_number] => 11/313631 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5158 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332400.pdf [firstpage_image] =>[orig_patent_app_number] => 11313631 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313631
Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance Dec 20, 2005 Issued
Array ( [id] => 5785706 [patent_doc_number] => 20060205208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Method for manufacturing a semiconductor device and method for etching the same' [patent_app_type] => utility [patent_app_number] => 11/306205 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8362 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205208.pdf [firstpage_image] =>[orig_patent_app_number] => 11306205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/306205
Method for manufacturing a semiconductor device and method for etching the same Dec 19, 2005 Abandoned
Array ( [id] => 5685996 [patent_doc_number] => 20060284311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'METHOD OF MANUFACTURING SELF-ALIGNED CONTACT OPENINGS AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/306095 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20060284311.pdf [firstpage_image] =>[orig_patent_app_number] => 11306095 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/306095
METHOD OF MANUFACTURING SELF-ALIGNED CONTACT OPENINGS AND SEMICONDUCTOR DEVICE Dec 14, 2005 Abandoned
Array ( [id] => 917026 [patent_doc_number] => 07323385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Method of fabricating flash memory device' [patent_app_type] => utility [patent_app_number] => 11/294915 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1766 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323385.pdf [firstpage_image] =>[orig_patent_app_number] => 11294915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/294915
Method of fabricating flash memory device Dec 5, 2005 Issued
Array ( [id] => 404620 [patent_doc_number] => 07288449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation' [patent_app_type] => utility [patent_app_number] => 11/286406 [patent_app_country] => US [patent_app_date] => 2005-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 2865 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288449.pdf [firstpage_image] =>[orig_patent_app_number] => 11286406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286406
Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation Nov 24, 2005 Issued
Array ( [id] => 4843305 [patent_doc_number] => 20080179713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Etching Technique For Creation of Thermally-Isolated Microstructures' [patent_app_type] => utility [patent_app_number] => 11/667008 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9223 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179713.pdf [firstpage_image] =>[orig_patent_app_number] => 11667008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/667008
Etching technique for creation of thermally-isolated microstructures Nov 9, 2005 Issued
Array ( [id] => 5823726 [patent_doc_number] => 20060060908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/270156 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9427 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060908.pdf [firstpage_image] =>[orig_patent_app_number] => 11270156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270156
Semiconductor device and method for manufacturing the same Nov 8, 2005 Issued
Array ( [id] => 5828307 [patent_doc_number] => 20060063333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Method of manufacturing split gate type nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 11/262767 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3965 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063333.pdf [firstpage_image] =>[orig_patent_app_number] => 11262767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/262767
Method of manufacturing split gate type nonvolatile memory device Oct 31, 2005 Issued
Array ( [id] => 1077254 [patent_doc_number] => 07615770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Integrated circuit having an insulated memory' [patent_app_type] => utility [patent_app_number] => 11/260346 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 12214 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615770.pdf [firstpage_image] =>[orig_patent_app_number] => 11260346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260346
Integrated circuit having an insulated memory Oct 26, 2005 Issued
Array ( [id] => 797953 [patent_doc_number] => 07427540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Methods for fabricating array substrates' [patent_app_type] => utility [patent_app_number] => 11/257455 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 35 [patent_no_of_words] => 5204 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427540.pdf [firstpage_image] =>[orig_patent_app_number] => 11257455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257455
Methods for fabricating array substrates Oct 23, 2005 Issued
Array ( [id] => 380052 [patent_doc_number] => 07309625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method for fabricating metal oxide semiconductor with lightly doped drain' [patent_app_type] => utility [patent_app_number] => 11/256855 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 3434 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309625.pdf [firstpage_image] =>[orig_patent_app_number] => 11256855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256855
Method for fabricating metal oxide semiconductor with lightly doped drain Oct 23, 2005 Issued
Array ( [id] => 5038197 [patent_doc_number] => 20070090479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Controlling bond fronts in wafer-scale packaging' [patent_app_type] => utility [patent_app_number] => 11/254875 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1918 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090479.pdf [firstpage_image] =>[orig_patent_app_number] => 11254875 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254875
Controlling bond fronts in wafer-scale packaging Oct 19, 2005 Abandoned
Array ( [id] => 159262 [patent_doc_number] => 07674726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Parts for deposition reactors' [patent_app_type] => utility [patent_app_number] => 11/250795 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3968 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/674/07674726.pdf [firstpage_image] =>[orig_patent_app_number] => 11250795 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250795
Parts for deposition reactors Oct 12, 2005 Issued
Array ( [id] => 5191926 [patent_doc_number] => 20070080408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Method for forming a silicidated contact' [patent_app_type] => utility [patent_app_number] => 11/246516 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1693 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080408.pdf [firstpage_image] =>[orig_patent_app_number] => 11246516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246516
Method for forming a silicidated contact Oct 6, 2005 Abandoned
Array ( [id] => 5171943 [patent_doc_number] => 20070072376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies' [patent_app_type] => utility [patent_app_number] => 11/244955 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5709 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072376.pdf [firstpage_image] =>[orig_patent_app_number] => 11244955 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244955
Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies Oct 4, 2005 Abandoned
Array ( [id] => 366616 [patent_doc_number] => 07479459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Semiconductor device manufacturing method and semiconductor device manufacturing apparatus' [patent_app_type] => utility [patent_app_number] => 11/242905 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6513 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479459.pdf [firstpage_image] =>[orig_patent_app_number] => 11242905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242905
Semiconductor device manufacturing method and semiconductor device manufacturing apparatus Oct 4, 2005 Issued
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