Darlington Ly

Array ( [id] => 5634933 [patent_doc_number] => 20060065906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Method for manufacturing and semiconductor light emitting device' [patent_app_type] => utility [patent_app_number] => 11/237805 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5648 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20060065906.pdf [firstpage_image] =>[orig_patent_app_number] => 11237805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5677965 [patent_doc_number] => 20060183321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method for reduction of gap fill defects' [patent_app_type] => utility [patent_app_number] => 11/238886 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3088 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20060183321.pdf [firstpage_image] =>[orig_patent_app_number] => 11238886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 53868 [patent_doc_number] => 07767562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Method of implanting using a shadow effect' [patent_app_type] => utility [patent_app_number] => 11/235330 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2478 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/767/07767562.pdf [firstpage_image] =>[orig_patent_app_number] => 11235330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 299832 [patent_doc_number] => 07538031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method of manufacturing a wiring substrate and an electronic instrument' [patent_app_type] => utility [patent_app_number] => 11/235645 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 10643 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538031.pdf [firstpage_image] =>[orig_patent_app_number] => 11235645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5667165 [patent_doc_number] => 20060172515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Method of fabricating a structure in a material' [patent_app_type] => utility [patent_app_number] => 11/233545 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3557 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20060172515.pdf [firstpage_image] =>[orig_patent_app_number] => 11233545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5768033 [patent_doc_number] => 20060019442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Method of forming a capacitor' [patent_app_type] => utility [patent_app_number] => 11/234328 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3821 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20060019442.pdf [firstpage_image] =>[orig_patent_app_number] => 11234328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5634921 [patent_doc_number] => 20060065894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Thin film transistor array panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/232736 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 9325 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20060065894.pdf [firstpage_image] =>[orig_patent_app_number] => 11232736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 373316 [patent_doc_number] => 07473619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby' [patent_app_type] => utility [patent_app_number] => 11/232666 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7299 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473619.pdf [firstpage_image] =>[orig_patent_app_number] => 11232666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 576311 [patent_doc_number] => 07456058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-25 [patent_title] => 'Stressed MOS device and methods for its fabrication' [patent_app_type] => utility [patent_app_number] => 11/231405 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3538 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456058.pdf [firstpage_image] =>[orig_patent_app_number] => 11231405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5763127 [patent_doc_number] => 20060017066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Methods of base formation in a BiCMOS process' [patent_app_type] => utility [patent_app_number] => 11/231385 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5433 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20060017066.pdf [firstpage_image] =>[orig_patent_app_number] => 11231385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 914213 [patent_doc_number] => 07326588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Image sensor with light guides' [patent_app_type] => utility [patent_app_number] => 11/229655 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4024 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/326/07326588.pdf [firstpage_image] =>[orig_patent_app_number] => 11229655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5104444 [patent_doc_number] => 20070063319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Film stack and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/229796 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1911 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063319.pdf [firstpage_image] =>[orig_patent_app_number] => 11229796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 583547 [patent_doc_number] => 07446006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Semiconductor fabrication process including silicide stringer removal processing' [patent_app_type] => utility [patent_app_number] => 11/226826 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2815 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446006.pdf [firstpage_image] =>[orig_patent_app_number] => 11226826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 422130 [patent_doc_number] => 07274062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Non-volatile memory and fabricating method and operating method thereof' [patent_app_type] => utility [patent_app_number] => 11/162116 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7096 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274062.pdf [firstpage_image] =>[orig_patent_app_number] => 11162116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6931291 [patent_doc_number] => 20050282326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Method for fabricating dual-metal gate device' [patent_app_type] => utility [patent_app_number] => 11/211798 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3682 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282326.pdf [firstpage_image] =>[orig_patent_app_number] => 11211798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4999950 [patent_doc_number] => 20070042584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'METHOD OF FORMING A SILICIDE' [patent_app_type] => utility [patent_app_number] => 11/161756 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3348 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042584.pdf [firstpage_image] =>[orig_patent_app_number] => 11161756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 404625 [patent_doc_number] => 07288454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 11/195086 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 9890 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288454.pdf [firstpage_image] =>[orig_patent_app_number] => 11195086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 525162 [patent_doc_number] => 07183149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Method of manufacturing field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/180726 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2726 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183149.pdf [firstpage_image] =>[orig_patent_app_number] => 11180726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 902979 [patent_doc_number] => 07335560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Methods of forming a nonvolatile memory device having a local SONOS structure that uses spacers to adjust the overlap between a gate electrode and a charge trapping layer' [patent_app_type] => utility [patent_app_number] => 11/168895 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3703 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335560.pdf [firstpage_image] =>[orig_patent_app_number] => 11168895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 377021 [patent_doc_number] => 07312121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/155174 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5077 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312121.pdf [firstpage_image] =>[orig_patent_app_number] => 11155174 [rel_patent_id] =>[rel_patent_doc_number] =>)