
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5616977
[patent_doc_number] => 20060186509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'Shallow trench isolation structure with active edge isolation'
[patent_app_type] => utility
[patent_app_number] => 11/064556
[patent_app_country] => US
[patent_app_date] => 2005-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2732
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20060186509.pdf
[firstpage_image] =>[orig_patent_app_number] => 11064556
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/064556 | Shallow trench isolation structure with active edge isolation | Feb 23, 2005 | Abandoned |
Array
(
[id] => 637814
[patent_doc_number] => 07125766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-24
[patent_title] => 'Method of forming capacitor for semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/062546
[patent_app_country] => US
[patent_app_date] => 2005-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5593
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/125/07125766.pdf
[firstpage_image] =>[orig_patent_app_number] => 11062546
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/062546 | Method of forming capacitor for semiconductor device | Feb 22, 2005 | Issued |
Array
(
[id] => 7072722
[patent_doc_number] => 20050145988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/058295
[patent_app_country] => US
[patent_app_date] => 2005-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4993
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20050145988.pdf
[firstpage_image] =>[orig_patent_app_number] => 11058295
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/058295 | Semiconductor device and method of fabricating the same | Feb 15, 2005 | Abandoned |
Array
(
[id] => 6910001
[patent_doc_number] => 20050173759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-11
[patent_title] => 'Fin FET and method of fabricating same'
[patent_app_type] => utility
[patent_app_number] => 11/050915
[patent_app_country] => US
[patent_app_date] => 2005-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3542
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20050173759.pdf
[firstpage_image] =>[orig_patent_app_number] => 11050915
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/050915 | Fin FET and method of fabricating same | Feb 3, 2005 | Issued |
Array
(
[id] => 582051
[patent_doc_number] => 07449396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Wafer dividing method'
[patent_app_type] => utility
[patent_app_number] => 11/047585
[patent_app_country] => US
[patent_app_date] => 2005-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 6007
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/449/07449396.pdf
[firstpage_image] =>[orig_patent_app_number] => 11047585
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/047585 | Wafer dividing method | Feb 1, 2005 | Issued |
Array
(
[id] => 7097912
[patent_doc_number] => 20050130371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Method of fabricating semiconductor device having capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/048995
[patent_app_country] => US
[patent_app_date] => 2005-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4987
[patent_no_of_claims] => 8
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20050130371.pdf
[firstpage_image] =>[orig_patent_app_number] => 11048995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/048995 | Method of fabricating semiconductor device having capacitor | Feb 1, 2005 | Issued |
Array
(
[id] => 9414275
[patent_doc_number] => 08698312
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-15
[patent_title] => 'Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging'
[patent_app_type] => utility
[patent_app_number] => 11/046986
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6755
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11046986
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/046986 | Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging | Jan 30, 2005 | Issued |
Array
(
[id] => 228741
[patent_doc_number] => 07601554
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-10-13
[patent_title] => 'Shaped MEMS contact'
[patent_app_type] => utility
[patent_app_number] => 11/047345
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 22
[patent_no_of_words] => 4724
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/601/07601554.pdf
[firstpage_image] =>[orig_patent_app_number] => 11047345
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/047345 | Shaped MEMS contact | Jan 30, 2005 | Issued |
Array
(
[id] => 5664708
[patent_doc_number] => 20060170058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Amorphous carbon contact film for contact hole etch process'
[patent_app_type] => utility
[patent_app_number] => 11/048485
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2709
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20060170058.pdf
[firstpage_image] =>[orig_patent_app_number] => 11048485
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/048485 | Amorphous carbon contact film for contact hole etch process | Jan 30, 2005 | Issued |
Array
(
[id] => 6949883
[patent_doc_number] => 20050224977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Wiring substrate and method using the same'
[patent_app_type] => utility
[patent_app_number] => 11/044716
[patent_app_country] => US
[patent_app_date] => 2005-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5579
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20050224977.pdf
[firstpage_image] =>[orig_patent_app_number] => 11044716
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/044716 | Wiring substrate and method using the same | Jan 27, 2005 | Abandoned |
Array
(
[id] => 7039552
[patent_doc_number] => 20050158951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Methods of fabricating semiconductor memory devices including different dielectric layers for the cell transistors and refresh transistors thereof'
[patent_app_type] => utility
[patent_app_number] => 11/042495
[patent_app_country] => US
[patent_app_date] => 2005-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158951.pdf
[firstpage_image] =>[orig_patent_app_number] => 11042495
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/042495 | Methods of fabricating semiconductor memory devices including different dielectric layers for the cell transistors and refresh transistors thereof | Jan 24, 2005 | Issued |
Array
(
[id] => 7069655
[patent_doc_number] => 20050245040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide'
[patent_app_type] => utility
[patent_app_number] => 11/039843
[patent_app_country] => US
[patent_app_date] => 2005-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20050245040.pdf
[firstpage_image] =>[orig_patent_app_number] => 11039843
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/039843 | Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide | Jan 23, 2005 | Abandoned |
Array
(
[id] => 907143
[patent_doc_number] => 07332419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-19
[patent_title] => 'Structure and method of fabricating a transistor having a trench gate'
[patent_app_type] => utility
[patent_app_number] => 11/038985
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/332/07332419.pdf
[firstpage_image] =>[orig_patent_app_number] => 11038985
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/038985 | Structure and method of fabricating a transistor having a trench gate | Jan 19, 2005 | Issued |
Array
(
[id] => 7178831
[patent_doc_number] => 20050124137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Semiconductor substrate and manufacturing method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/039285
[patent_app_country] => US
[patent_app_date] => 2005-01-19
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[pdf_file] => publications/A1/0124/20050124137.pdf
[firstpage_image] =>[orig_patent_app_number] => 11039285
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/039285 | Semiconductor substrate and manufacturing method therefor | Jan 18, 2005 | Abandoned |
Array
(
[id] => 228777
[patent_doc_number] => 07601590
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-13
[patent_title] => 'Electronic memory circuit and related manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/033776
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[pdf_file] => patents/07/601/07601590.pdf
[firstpage_image] =>[orig_patent_app_number] => 11033776
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/033776 | Electronic memory circuit and related manufacturing method | Jan 11, 2005 | Issued |
Array
(
[id] => 916950
[patent_doc_number] => 07323348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-29
[patent_title] => 'Superconducting integrated circuit and method for fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 11/031995
[patent_app_country] => US
[patent_app_date] => 2005-01-11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/323/07323348.pdf
[firstpage_image] =>[orig_patent_app_number] => 11031995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/031995 | Superconducting integrated circuit and method for fabrication thereof | Jan 10, 2005 | Issued |
Array
(
[id] => 5694295
[patent_doc_number] => 20060154442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide'
[patent_app_type] => utility
[patent_app_number] => 11/031165
[patent_app_country] => US
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[pdf_file] => publications/A1/0154/20060154442.pdf
[firstpage_image] =>[orig_patent_app_number] => 11031165
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/031165 | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide | Jan 6, 2005 | Issued |
Array
(
[id] => 856748
[patent_doc_number] => 07375007
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[patent_issue_date] => 2008-05-20
[patent_title] => 'Method of manufacturing a semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 11030165
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/030165 | Method of manufacturing a semiconductor device | Jan 6, 2005 | Issued |
Array
(
[id] => 370151
[patent_doc_number] => 07476926
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[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Eraseable nonvolatile memory with sidewall storage'
[patent_app_type] => utility
[patent_app_number] => 10/905475
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[pdf_file] => patents/07/476/07476926.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905475
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905475 | Eraseable nonvolatile memory with sidewall storage | Jan 5, 2005 | Issued |
Array
(
[id] => 485535
[patent_doc_number] => 07217620
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/027516
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/217/07217620.pdf
[firstpage_image] =>[orig_patent_app_number] => 11027516
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/027516 | Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same | Dec 29, 2004 | Issued |