Darlington Ly

Array ( [id] => 7005283 [patent_doc_number] => 20050170596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/024845 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4780 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170596.pdf [firstpage_image] =>[orig_patent_app_number] => 11024845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 788106 [patent_doc_number] => 06987038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Method for fabricating MOS field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/024846 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1818 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987038.pdf [firstpage_image] =>[orig_patent_app_number] => 11024846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6983441 [patent_doc_number] => 20050153511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Methods of fabricating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 11/024436 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2383 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153511.pdf [firstpage_image] =>[orig_patent_app_number] => 11024436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253263 [patent_doc_number] => 20050142722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method for fabricating gate electrode of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/026925 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1385 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142722.pdf [firstpage_image] =>[orig_patent_app_number] => 11026925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253302 [patent_doc_number] => 20050142736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Methods of fabricating semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/027076 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1507 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142736.pdf [firstpage_image] =>[orig_patent_app_number] => 11027076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5652923 [patent_doc_number] => 20060138658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Carbon nanotube interconnects in porous diamond interlayer dielectrics' [patent_app_type] => utility [patent_app_number] => 11/026315 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3472 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138658.pdf [firstpage_image] =>[orig_patent_app_number] => 11026315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7235927 [patent_doc_number] => 20050139895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Non-volatile memory device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/026826 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139895.pdf [firstpage_image] =>[orig_patent_app_number] => 11026826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253414 [patent_doc_number] => 20050142760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/022656 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1892 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142760.pdf [firstpage_image] =>[orig_patent_app_number] => 11022656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253295 [patent_doc_number] => 20050142734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Isolation methods in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/024636 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1628 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142734.pdf [firstpage_image] =>[orig_patent_app_number] => 11024636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7170525 [patent_doc_number] => 20050202635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Method for fabricating vertical transistor' [patent_app_type] => utility [patent_app_number] => 11/020095 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2235 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20050202635.pdf [firstpage_image] =>[orig_patent_app_number] => 11020095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6983428 [patent_doc_number] => 20050153498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method of manufacturing p-channel MOS transistor and CMOS transistor' [patent_app_type] => utility [patent_app_number] => 11/020096 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153498.pdf [firstpage_image] =>[orig_patent_app_number] => 11020096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253349 [patent_doc_number] => 20050142746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of fabricating flash memory device' [patent_app_type] => utility [patent_app_number] => 11/019315 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2291 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142746.pdf [firstpage_image] =>[orig_patent_app_number] => 11019315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5656044 [patent_doc_number] => 20060141780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Methods for the plasma formation of a microelectronic barrier layer' [patent_app_type] => utility [patent_app_number] => 11/022216 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2290 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141780.pdf [firstpage_image] =>[orig_patent_app_number] => 11022216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7048448 [patent_doc_number] => 20050184335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Semiconductor device and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/021056 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2347 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184335.pdf [firstpage_image] =>[orig_patent_app_number] => 11021056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7236134 [patent_doc_number] => 20050139925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Laser mask and crystallization method using the same' [patent_app_type] => utility [patent_app_number] => 11/013876 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12347 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139925.pdf [firstpage_image] =>[orig_patent_app_number] => 11013876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 415211 [patent_doc_number] => 07279394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Method for forming wall oxide layer and isolation layer in flash memory device' [patent_app_type] => utility [patent_app_number] => 11/016436 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3118 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279394.pdf [firstpage_image] =>[orig_patent_app_number] => 11016436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5881053 [patent_doc_number] => 20060030136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'METHOD OF FABRICATING A GATE OXIDE LAYER' [patent_app_type] => utility [patent_app_number] => 10/905086 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20060030136.pdf [firstpage_image] =>[orig_patent_app_number] => 10905086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5743252 [patent_doc_number] => 20060088977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method of forming an isolation layer in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/010755 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1798 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20060088977.pdf [firstpage_image] =>[orig_patent_app_number] => 11010755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 270423 [patent_doc_number] => 07563659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same' [patent_app_type] => utility [patent_app_number] => 11/003326 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3537 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563659.pdf [firstpage_image] =>[orig_patent_app_number] => 11003326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4816856 [patent_doc_number] => 20080224115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Fabricating a Set of Semiconducting Nanowires, and Electric Device Comprising a Set of Nanowires' [patent_app_type] => utility [patent_app_number] => 10/584037 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13714 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224115.pdf [firstpage_image] =>[orig_patent_app_number] => 10584037 [rel_patent_id] =>[rel_patent_doc_number] =>)