Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 757642 [patent_doc_number] => 07015099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method of manufacturing a flash memory cell capable of increasing a coupling ratio' [patent_app_type] => utility [patent_app_number] => 11/004301 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3870 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015099.pdf [firstpage_image] =>[orig_patent_app_number] => 11004301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/004301
Method of manufacturing a flash memory cell capable of increasing a coupling ratio Dec 2, 2004 Issued
Array ( [id] => 5913068 [patent_doc_number] => 20060128130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Method for fabricating recessed gate structure' [patent_app_type] => utility [patent_app_number] => 11/003755 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1659 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128130.pdf [firstpage_image] =>[orig_patent_app_number] => 11003755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003755
Method for fabricating recessed gate structure Dec 1, 2004 Abandoned
Array ( [id] => 972122 [patent_doc_number] => 06936507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Method of forming field effect transistors' [patent_app_type] => utility [patent_app_number] => 11/001145 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3774 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936507.pdf [firstpage_image] =>[orig_patent_app_number] => 11001145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/001145
Method of forming field effect transistors Nov 29, 2004 Issued
Array ( [id] => 7140089 [patent_doc_number] => 20050116274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Semiconductor device having isolation pattern in interlayer insulating layer between capacitor contact plugs and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/001596 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4103 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116274.pdf [firstpage_image] =>[orig_patent_app_number] => 11001596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/001596
Semiconductor device having isolation pattern in interlayer insulating layer between capacitor contact plugs and methods of fabricating the same Nov 29, 2004 Issued
Array ( [id] => 6918195 [patent_doc_number] => 20050095756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Method of forming a field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/000588 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3721 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095756.pdf [firstpage_image] =>[orig_patent_app_number] => 11000588 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000588
Method of forming a field effect transistor Nov 29, 2004 Issued
Array ( [id] => 5895002 [patent_doc_number] => 20060003541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method for forming device isolation film of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/998806 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1504 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003541.pdf [firstpage_image] =>[orig_patent_app_number] => 10998806 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998806
Method for forming device isolation film of semiconductor device Nov 29, 2004 Abandoned
Array ( [id] => 557360 [patent_doc_number] => 07470576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Methods of forming field effect transistor gate lines' [patent_app_type] => utility [patent_app_number] => 11/000786 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3782 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/470/07470576.pdf [firstpage_image] =>[orig_patent_app_number] => 11000786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000786
Methods of forming field effect transistor gate lines Nov 29, 2004 Issued
Array ( [id] => 7617106 [patent_doc_number] => 06946335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Method of manufacturing improved double-diffused metal-oxide-semiconductor device with self-aligned channel' [patent_app_type] => utility [patent_app_number] => 10/995166 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1427 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946335.pdf [firstpage_image] =>[orig_patent_app_number] => 10995166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995166
Method of manufacturing improved double-diffused metal-oxide-semiconductor device with self-aligned channel Nov 23, 2004 Issued
Array ( [id] => 7169039 [patent_doc_number] => 20050121705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method and apparatus for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/989385 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5399 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121705.pdf [firstpage_image] =>[orig_patent_app_number] => 10989385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989385
Method and apparatus for fabricating semiconductor device Nov 16, 2004 Abandoned
Array ( [id] => 292266 [patent_doc_number] => 07544556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-09 [patent_title] => 'Process for forming CMOS devices using removable spacers' [patent_app_type] => utility [patent_app_number] => 10/986636 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4439 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/544/07544556.pdf [firstpage_image] =>[orig_patent_app_number] => 10986636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986636
Process for forming CMOS devices using removable spacers Nov 11, 2004 Issued
Array ( [id] => 766245 [patent_doc_number] => 07008835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance' [patent_app_type] => utility [patent_app_number] => 10/985246 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5132 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/008/07008835.pdf [firstpage_image] =>[orig_patent_app_number] => 10985246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985246
Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance Nov 9, 2004 Issued
Array ( [id] => 951314 [patent_doc_number] => 06960516 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'Semiconductor device and fabrication process thereof' [patent_app_type] => utility [patent_app_number] => 10/981556 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4396 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960516.pdf [firstpage_image] =>[orig_patent_app_number] => 10981556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981556
Semiconductor device and fabrication process thereof Nov 4, 2004 Issued
Array ( [id] => 4451116 [patent_doc_number] => 07964439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Methods of fabricating devices by transfer of organic material' [patent_app_type] => utility [patent_app_number] => 10/979448 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 18075 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964439.pdf [firstpage_image] =>[orig_patent_app_number] => 10979448 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979448
Methods of fabricating devices by transfer of organic material Nov 2, 2004 Issued
Array ( [id] => 823552 [patent_doc_number] => 07405123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/980075 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6577 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405123.pdf [firstpage_image] =>[orig_patent_app_number] => 10980075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980075
Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof Nov 1, 2004 Issued
Array ( [id] => 946566 [patent_doc_number] => 06964898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'Method for fabricating deep trench capacitor' [patent_app_type] => utility [patent_app_number] => 10/904186 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 4343 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964898.pdf [firstpage_image] =>[orig_patent_app_number] => 10904186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904186
Method for fabricating deep trench capacitor Oct 27, 2004 Issued
Array ( [id] => 7161986 [patent_doc_number] => 20050085048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Method of fabricating shallow trench isolation with improved smiling effect' [patent_app_type] => utility [patent_app_number] => 10/967155 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1159 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20050085048.pdf [firstpage_image] =>[orig_patent_app_number] => 10967155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/967155
Method of fabricating shallow trench isolation with improved smiling effect Oct 18, 2004 Abandoned
Array ( [id] => 7235068 [patent_doc_number] => 20050079673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/954835 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5058 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20050079673.pdf [firstpage_image] =>[orig_patent_app_number] => 10954835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954835
Method of manufacturing a semiconductor memory device Sep 28, 2004 Issued
Array ( [id] => 190853 [patent_doc_number] => 07642164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-05 [patent_title] => 'Method of forming self aligned contacts for a power MOSFET' [patent_app_type] => utility [patent_app_number] => 10/951831 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5357 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642164.pdf [firstpage_image] =>[orig_patent_app_number] => 10951831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/951831
Method of forming self aligned contacts for a power MOSFET Sep 26, 2004 Issued
Array ( [id] => 6918224 [patent_doc_number] => 20050095785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Method of manufacturing split gate type nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 10/948155 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095785.pdf [firstpage_image] =>[orig_patent_app_number] => 10948155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/948155
Method of manufacturing split gate type nonvolatile memory device having self-aligned spacer type control gate Sep 23, 2004 Issued
Array ( [id] => 7136871 [patent_doc_number] => 20050181556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Method of forming a semiconductor device having a capacitor and a resistor' [patent_app_type] => utility [patent_app_number] => 10/945147 [patent_app_country] => US [patent_app_date] => 2004-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1327 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181556.pdf [firstpage_image] =>[orig_patent_app_number] => 10945147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/945147
Method of forming a semiconductor device having a capacitor and a resistor Sep 19, 2004 Issued
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