
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7033883
[patent_doc_number] => 20050032393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Method of composite gate formation'
[patent_app_type] => utility
[patent_app_number] => 10/932130
[patent_app_country] => US
[patent_app_date] => 2004-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2961
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 31
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20050032393.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932130
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932130 | Method of composite gate formation | Aug 31, 2004 | Abandoned |
Array
(
[id] => 7612856
[patent_doc_number] => 06902978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Method of making the selection gate in a split-gate flash EEPROM cell and its structure'
[patent_app_type] => utility
[patent_app_number] => 10/929396
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3009
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/902/06902978.pdf
[firstpage_image] =>[orig_patent_app_number] => 10929396
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929396 | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | Aug 30, 2004 | Issued |
Array
(
[id] => 7154709
[patent_doc_number] => 20050026368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Method of making the selection gate in a split-gate flash EEPROM cell its and structure'
[patent_app_type] => utility
[patent_app_number] => 10/929397
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2981
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[pdf_file] => publications/A1/0026/20050026368.pdf
[firstpage_image] =>[orig_patent_app_number] => 10929397
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929397 | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | Aug 30, 2004 | Issued |
Array
(
[id] => 9401595
[patent_doc_number] => 08691647
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-04-08
[patent_title] => 'Memory devices containing a high-K dielectric layer'
[patent_app_type] => utility
[patent_app_number] => 10/927692
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 8146
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10927692
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/927692 | Memory devices containing a high-K dielectric layer | Aug 26, 2004 | Issued |
Array
(
[id] => 7002464
[patent_doc_number] => 20050167777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Microelectronic device with active layer bumper'
[patent_app_type] => utility
[patent_app_number] => 10/917196
[patent_app_country] => US
[patent_app_date] => 2004-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1989
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0167/20050167777.pdf
[firstpage_image] =>[orig_patent_app_number] => 10917196
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/917196 | Microelectronic device with active layer bumper | Aug 11, 2004 | Abandoned |
Array
(
[id] => 7120335
[patent_doc_number] => 20050012164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'High k oxide'
[patent_app_type] => utility
[patent_app_number] => 10/917886
[patent_app_country] => US
[patent_app_date] => 2004-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1275
[patent_no_of_claims] => 17
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20050012164.pdf
[firstpage_image] =>[orig_patent_app_number] => 10917886
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/917886 | Bonding gate oxide with high-k additives | Aug 11, 2004 | Issued |
Array
(
[id] => 662659
[patent_doc_number] => 07101755
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'Gate conductor isolation and method for manufacturing same'
[patent_app_type] => utility
[patent_app_number] => 10/912005
[patent_app_country] => US
[patent_app_date] => 2004-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1809
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/101/07101755.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912005
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912005 | Gate conductor isolation and method for manufacturing same | Aug 4, 2004 | Issued |
Array
(
[id] => 7086599
[patent_doc_number] => 20050006711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Method and system for forming dual work function gate electrodes in a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/911165
[patent_app_country] => US
[patent_app_date] => 2004-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2808
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20050006711.pdf
[firstpage_image] =>[orig_patent_app_number] => 10911165
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911165 | Method and system for forming dual work function gate electrodes in a semiconductor device | Aug 3, 2004 | Issued |
Array
(
[id] => 5820650
[patent_doc_number] => 20060024963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'Metal-germanium physical vapor deposition for semiconductor device defect reduction'
[patent_app_type] => utility
[patent_app_number] => 10/903716
[patent_app_country] => US
[patent_app_date] => 2004-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3522
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20060024963.pdf
[firstpage_image] =>[orig_patent_app_number] => 10903716
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/903716 | Metal-germanium physical vapor deposition for semiconductor device defect reduction | Jul 29, 2004 | Issued |
Array
(
[id] => 267091
[patent_doc_number] => 07566616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Methods for fabricating flash memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/902543
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 1767
[patent_no_of_claims] => 9
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/566/07566616.pdf
[firstpage_image] =>[orig_patent_app_number] => 10902543
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/902543 | Methods for fabricating flash memory devices | Jul 28, 2004 | Issued |
Array
(
[id] => 7072648
[patent_doc_number] => 20050145914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Semiconductor device having trench capacitor and fabrication method for the same'
[patent_app_type] => utility
[patent_app_number] => 10/892496
[patent_app_country] => US
[patent_app_date] => 2004-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[patent_no_of_words] => 5879
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20050145914.pdf
[firstpage_image] =>[orig_patent_app_number] => 10892496
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892496 | Semiconductor device having trench capacitor and fabrication method for the same | Jul 15, 2004 | Abandoned |
Array
(
[id] => 553147
[patent_doc_number] => 07470291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-30
[patent_title] => 'Production process of ceramic electronic component'
[patent_app_type] => utility
[patent_app_number] => 10/567436
[patent_app_country] => US
[patent_app_date] => 2004-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/07/470/07470291.pdf
[firstpage_image] =>[orig_patent_app_number] => 10567436
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/567436 | Production process of ceramic electronic component | Jul 12, 2004 | Issued |
Array
(
[id] => 6975460
[patent_doc_number] => 20050285175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Vertical SOI Device'
[patent_app_type] => utility
[patent_app_number] => 10/710166
[patent_app_country] => US
[patent_app_date] => 2004-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => publications/A1/0285/20050285175.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710166
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710166 | Vertical SOI Device | Jun 22, 2004 | Abandoned |
Array
(
[id] => 7010922
[patent_doc_number] => 20050064638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Method for the selective formation of a silicide on a wafer'
[patent_app_type] => utility
[patent_app_number] => 10/871356
[patent_app_country] => US
[patent_app_date] => 2004-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20050064638.pdf
[firstpage_image] =>[orig_patent_app_number] => 10871356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/871356 | Method for the selective formation of a silicide on a wafer using an implantation residue layer | Jun 17, 2004 | Issued |
Array
(
[id] => 7089136
[patent_doc_number] => 20050009249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Method for fabricating polycrystalline silicon liquid crystal display device'
[patent_app_type] => utility
[patent_app_number] => 10/867814
[patent_app_country] => US
[patent_app_date] => 2004-06-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0009/20050009249.pdf
[firstpage_image] =>[orig_patent_app_number] => 10867814
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/867814 | Method for fabricating polycrystalline silicon liquid crystal display device | Jun 15, 2004 | Issued |
Array
(
[id] => 7056087
[patent_doc_number] => 20050277262
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Method for manufacturing isolation structures in a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/867336
[patent_app_country] => US
[patent_app_date] => 2004-06-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0277/20050277262.pdf
[firstpage_image] =>[orig_patent_app_number] => 10867336
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/867336 | Method for manufacturing isolation structures in a semiconductor device | Jun 13, 2004 | Abandoned |
Array
(
[id] => 1059500
[patent_doc_number] => 06852590
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-08
[patent_title] => 'Deep trench capacitor and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/709926
[patent_app_country] => US
[patent_app_date] => 2004-06-07
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/852/06852590.pdf
[firstpage_image] =>[orig_patent_app_number] => 10709926
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709926 | Deep trench capacitor and method of fabricating the same | Jun 6, 2004 | Issued |
Array
(
[id] => 1043663
[patent_doc_number] => 06867096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-15
[patent_title] => 'Method of fabricating semiconductor device having capacitor'
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[patent_app_number] => 10/855165
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[pdf_file] => patents/06/867/06867096.pdf
[firstpage_image] =>[orig_patent_app_number] => 10855165
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/855165 | Method of fabricating semiconductor device having capacitor | May 26, 2004 | Issued |
Array
(
[id] => 7264079
[patent_doc_number] => 20040241956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Methods of forming trench isolation regions using chemical mechanical polishing and etching'
[patent_app_type] => new
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[pdf_file] => publications/A1/0241/20040241956.pdf
[firstpage_image] =>[orig_patent_app_number] => 10851716
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/851716 | Methods of forming trench isolation regions using chemical mechanical polishing and etching | May 20, 2004 | Abandoned |
Array
(
[id] => 7342185
[patent_doc_number] => 20040246648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Capacitance-type dynamic-quantity sensor and manufacturing method therefor'
[patent_app_type] => new
[patent_app_number] => 10/848285
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20040246648.pdf
[firstpage_image] =>[orig_patent_app_number] => 10848285
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/848285 | Capacitance-type dynamic-quantity sensor and manufacturing method therefor | May 17, 2004 | Issued |