
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 556920
[patent_doc_number] => 07157317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Manufacturing method for field-effect transistor'
[patent_app_type] => utility
[patent_app_number] => 10/844143
[patent_app_country] => US
[patent_app_date] => 2004-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 37
[patent_no_of_words] => 12870
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/157/07157317.pdf
[firstpage_image] =>[orig_patent_app_number] => 10844143
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/844143 | Manufacturing method for field-effect transistor | May 11, 2004 | Issued |
Array
(
[id] => 7275800
[patent_doc_number] => 20040235251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric'
[patent_app_type] => new
[patent_app_number] => 10/840964
[patent_app_country] => US
[patent_app_date] => 2004-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2580
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20040235251.pdf
[firstpage_image] =>[orig_patent_app_number] => 10840964
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/840964 | Method for making a semiconductor device having a high-k gate dielectric | May 6, 2004 | Issued |
Array
(
[id] => 163199
[patent_doc_number] => 07671427
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method of manufacturing film bulk acoustic resonator using internal stress of metallic film and resonator manufactured thereby'
[patent_app_type] => utility
[patent_app_number] => 10/838326
[patent_app_country] => US
[patent_app_date] => 2004-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 3775
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/671/07671427.pdf
[firstpage_image] =>[orig_patent_app_number] => 10838326
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/838326 | Method of manufacturing film bulk acoustic resonator using internal stress of metallic film and resonator manufactured thereby | May 4, 2004 | Issued |
Array
(
[id] => 7429146
[patent_doc_number] => 20040209428
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Split gate flash memory device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/835036
[patent_app_country] => US
[patent_app_date] => 2004-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 3417
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20040209428.pdf
[firstpage_image] =>[orig_patent_app_number] => 10835036
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/835036 | Split gate flash memory device and method of fabricating the same | Apr 27, 2004 | Abandoned |
Array
(
[id] => 1043658
[patent_doc_number] => 06867091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-15
[patent_title] => 'Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide'
[patent_app_type] => utility
[patent_app_number] => 10/833066
[patent_app_country] => US
[patent_app_date] => 2004-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2251
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/867/06867091.pdf
[firstpage_image] =>[orig_patent_app_number] => 10833066
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/833066 | Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide | Apr 27, 2004 | Issued |
Array
(
[id] => 7296458
[patent_doc_number] => 20040214382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Method of manufacturing MOS transistor having short channel'
[patent_app_type] => new
[patent_app_number] => 10/834306
[patent_app_country] => US
[patent_app_date] => 2004-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3146
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20040214382.pdf
[firstpage_image] =>[orig_patent_app_number] => 10834306
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834306 | Method of manufacturing MOS transistor having short channel | Apr 26, 2004 | Abandoned |
Array
(
[id] => 1065562
[patent_doc_number] => 06846713
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-25
[patent_title] => 'Method for manufacturing a nonvolatile memory transistor'
[patent_app_type] => utility
[patent_app_number] => 10/827456
[patent_app_country] => US
[patent_app_date] => 2004-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 1864
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 305
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/846/06846713.pdf
[firstpage_image] =>[orig_patent_app_number] => 10827456
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/827456 | Method for manufacturing a nonvolatile memory transistor | Apr 18, 2004 | Issued |
Array
(
[id] => 7379966
[patent_doc_number] => 20040179389
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices'
[patent_app_type] => new
[patent_app_number] => 10/810884
[patent_app_country] => US
[patent_app_date] => 2004-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 13745
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20040179389.pdf
[firstpage_image] =>[orig_patent_app_number] => 10810884
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/810884 | Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices | Mar 28, 2004 | Issued |
Array
(
[id] => 6958628
[patent_doc_number] => 20050214998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Local stress control for CMOS performance enhancement'
[patent_app_type] => utility
[patent_app_number] => 10/810795
[patent_app_country] => US
[patent_app_date] => 2004-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3181
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20050214998.pdf
[firstpage_image] =>[orig_patent_app_number] => 10810795
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/810795 | Local stress control for CMOS performance enhancement | Mar 25, 2004 | Abandoned |
Array
(
[id] => 7406633
[patent_doc_number] => 20040175899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Method for fabricating silicon-on-insulator material'
[patent_app_type] => new
[patent_app_number] => 10/800998
[patent_app_country] => US
[patent_app_date] => 2004-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6535
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20040175899.pdf
[firstpage_image] =>[orig_patent_app_number] => 10800998
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/800998 | Method for fabricating silicon-on-insulator material | Mar 15, 2004 | Abandoned |
Array
(
[id] => 7229632
[patent_doc_number] => 20050255618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-17
[patent_title] => 'Display device producing method and display device producing device'
[patent_app_type] => utility
[patent_app_number] => 10/514756
[patent_app_country] => US
[patent_app_date] => 2004-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9489
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0255/20050255618.pdf
[firstpage_image] =>[orig_patent_app_number] => 10514756
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/514756 | Display device producing method and display device producing device | Mar 11, 2004 | Issued |
Array
(
[id] => 1027903
[patent_doc_number] => 06881618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Method of manufacturing a dual gate semiconductor device with a poly-metal electrode'
[patent_app_type] => utility
[patent_app_number] => 10/787436
[patent_app_country] => US
[patent_app_date] => 2004-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 5971
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/881/06881618.pdf
[firstpage_image] =>[orig_patent_app_number] => 10787436
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/787436 | Method of manufacturing a dual gate semiconductor device with a poly-metal electrode | Feb 26, 2004 | Issued |
Array
(
[id] => 1110907
[patent_doc_number] => 06806136
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-19
[patent_title] => 'Method of forming a semiconductor device having a capacitor and a resistor'
[patent_app_type] => B1
[patent_app_number] => 10/780416
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1318
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 318
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/806/06806136.pdf
[firstpage_image] =>[orig_patent_app_number] => 10780416
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/780416 | Method of forming a semiconductor device having a capacitor and a resistor | Feb 16, 2004 | Issued |
Array
(
[id] => 7010921
[patent_doc_number] => 20050064637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => '[METHOD OF MANUFACTURING NMOS TRANSISTOR WITH P-TYPE GATE]'
[patent_app_type] => utility
[patent_app_number] => 10/708175
[patent_app_country] => US
[patent_app_date] => 2004-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2118
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20050064637.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708175
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708175 | [METHOD OF MANUFACTURING NMOS TRANSISTOR WITH P-TYPE GATE] | Feb 12, 2004 | Abandoned |
Array
(
[id] => 968524
[patent_doc_number] => 06939798
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'Method for forming T-shaped conductor wires of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/775936
[patent_app_country] => US
[patent_app_date] => 2004-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2790
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/939/06939798.pdf
[firstpage_image] =>[orig_patent_app_number] => 10775936
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/775936 | Method for forming T-shaped conductor wires of semiconductor device | Feb 10, 2004 | Issued |
Array
(
[id] => 7462631
[patent_doc_number] => 20040198037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/774496
[patent_app_country] => US
[patent_app_date] => 2004-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5151
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20040198037.pdf
[firstpage_image] =>[orig_patent_app_number] => 10774496
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/774496 | Method for manufacturing a semiconductor device suitable for the formation of a wiring layer | Feb 9, 2004 | Issued |
Array
(
[id] => 7039532
[patent_doc_number] => 20050158937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 10/707841
[patent_app_country] => US
[patent_app_date] => 2004-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4079
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158937.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707841
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707841 | Method and structure for controlling stress in a transistor channel | Jan 15, 2004 | Issued |
Array
(
[id] => 568342
[patent_doc_number] => 07462549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-09
[patent_title] => 'Shallow trench isolation process and structure with minimized strained silicon consumption'
[patent_app_type] => utility
[patent_app_number] => 10/755602
[patent_app_country] => US
[patent_app_date] => 2004-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4108
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/462/07462549.pdf
[firstpage_image] =>[orig_patent_app_number] => 10755602
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/755602 | Shallow trench isolation process and structure with minimized strained silicon consumption | Jan 11, 2004 | Issued |
Array
(
[id] => 6983449
[patent_doc_number] => 20050153519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities'
[patent_app_type] => utility
[patent_app_number] => 10/753816
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8370
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20050153519.pdf
[firstpage_image] =>[orig_patent_app_number] => 10753816
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/753816 | Shallow trench isolation method for reducing oxide thickness variations at different pattern densities | Jan 7, 2004 | Issued |
Array
(
[id] => 881033
[patent_doc_number] => 07355214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-08
[patent_title] => 'Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 10/752705
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 10490
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/355/07355214.pdf
[firstpage_image] =>[orig_patent_app_number] => 10752705
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/752705 | Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate | Jan 7, 2004 | Issued |