Darlington Ly

Array ( [id] => 7275789 [patent_doc_number] => 20040235240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Method of fabricating memory device with vertical transistors and trench capacitors' [patent_app_type] => new [patent_app_number] => 10/639986 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2755 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20040235240.pdf [firstpage_image] =>[orig_patent_app_number] => 10639986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1141452 [patent_doc_number] => 06777295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method of fabricating trench power MOSFET' [patent_app_type] => B1 [patent_app_number] => 10/638346 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2549 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777295.pdf [firstpage_image] =>[orig_patent_app_number] => 10638346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7383295 [patent_doc_number] => 20040082141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method of fabricating a semiconductor device having trenches' [patent_app_type] => new [patent_app_number] => 10/635506 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4280 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082141.pdf [firstpage_image] =>[orig_patent_app_number] => 10635506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1115569 [patent_doc_number] => 06800525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Method of manufacturing split gate flash memory device' [patent_app_type] => B2 [patent_app_number] => 10/631186 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 35 [patent_no_of_words] => 3656 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800525.pdf [firstpage_image] =>[orig_patent_app_number] => 10631186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7675056 [patent_doc_number] => 20040127062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Methods of forming a nonvolatile memory device having a local SONOS structure that use spacers to adjust the overlap between a gate electrode and a charge trapping layer' [patent_app_type] => new [patent_app_number] => 10/625713 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3680 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20040127062.pdf [firstpage_image] =>[orig_patent_app_number] => 10625713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7383339 [patent_doc_number] => 20040082148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method of increasing the area of a useful layer of material transferred onto a support' [patent_app_type] => new [patent_app_number] => 10/619596 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6322 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082148.pdf [firstpage_image] =>[orig_patent_app_number] => 10619596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7409031 [patent_doc_number] => 20040106287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric' [patent_app_type] => new [patent_app_number] => 10/618226 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106287.pdf [firstpage_image] =>[orig_patent_app_number] => 10618226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138346 [patent_doc_number] => 06780742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Undulated moat for reducing contact resistance' [patent_app_type] => B1 [patent_app_number] => 10/613195 [patent_app_country] => US [patent_app_date] => 2003-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2634 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780742.pdf [firstpage_image] =>[orig_patent_app_number] => 10613195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7365686 [patent_doc_number] => 20040005750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Approach to prevent spacer undercut by low temperature nitridation' [patent_app_type] => new [patent_app_number] => 10/613606 [patent_app_country] => US [patent_app_date] => 2003-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3853 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005750.pdf [firstpage_image] =>[orig_patent_app_number] => 10613606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7360086 [patent_doc_number] => 20040014329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method for forming DRAM cell' [patent_app_type] => new [patent_app_number] => 10/608145 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1858 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014329.pdf [firstpage_image] =>[orig_patent_app_number] => 10608145 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7429653 [patent_doc_number] => 20040266129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'METHOD OF FORMING SILICON-ON-INSULATOR WAFERS HAVING PROCESS RESISTANT APPLICATIONS' [patent_app_type] => new [patent_app_number] => 10/604146 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266129.pdf [firstpage_image] =>[orig_patent_app_number] => 10604146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6636003 [patent_doc_number] => 20030211673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Dynamic random access memory with improved contact arrangements' [patent_app_type] => new [patent_app_number] => 10/455478 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 25406 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211673.pdf [firstpage_image] =>[orig_patent_app_number] => 10455478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6664285 [patent_doc_number] => 20030203611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Method of manufacturing a dual gate semiconductor device with a poly-metal electrode' [patent_app_type] => new [patent_app_number] => 10/448351 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5888 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203611.pdf [firstpage_image] =>[orig_patent_app_number] => 10448351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 468650 [patent_doc_number] => 07232717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'Method of manufacturing non-volatile DRAM' [patent_app_type] => utility [patent_app_number] => 10/447675 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 5995 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/232/07232717.pdf [firstpage_image] =>[orig_patent_app_number] => 10447675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6664248 [patent_doc_number] => 20030203574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Method of manufacturing nonvolatile memory cell' [patent_app_type] => new [patent_app_number] => 10/445982 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4082 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203574.pdf [firstpage_image] =>[orig_patent_app_number] => 10445982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6676905 [patent_doc_number] => 20030227045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Method of forming storage nodes comprising a base in a contact hole and related structures' [patent_app_type] => new [patent_app_number] => 10/445426 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6571 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227045.pdf [firstpage_image] =>[orig_patent_app_number] => 10445426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1110938 [patent_doc_number] => 06806146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric' [patent_app_type] => B1 [patent_app_number] => 10/441616 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2556 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806146.pdf [firstpage_image] =>[orig_patent_app_number] => 10441616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7203933 [patent_doc_number] => 20040087121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Method of forming a nickel silicide region in a doped silicon-containing semiconductor area' [patent_app_type] => new [patent_app_number] => 10/440656 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5789 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087121.pdf [firstpage_image] =>[orig_patent_app_number] => 10440656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1009324 [patent_doc_number] => 06900086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Semiconductor device having MISFETs' [patent_app_type] => utility [patent_app_number] => 10/435380 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 24085 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900086.pdf [firstpage_image] =>[orig_patent_app_number] => 10435380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7429414 [patent_doc_number] => 20040209468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Method for fabricating a gate structure of a field effect transistor' [patent_app_type] => new [patent_app_number] => 10/418995 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4408 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209468.pdf [firstpage_image] =>[orig_patent_app_number] => 10418995 [rel_patent_id] =>[rel_patent_doc_number] =>)