Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1256069 [patent_doc_number] => 06667209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Methods for forming semiconductor device capacitors that include an adhesive spacer that ensures stable operation' [patent_app_type] => B2 [patent_app_number] => 10/350766 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667209.pdf [firstpage_image] =>[orig_patent_app_number] => 10350766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/350766
Methods for forming semiconductor device capacitors that include an adhesive spacer that ensures stable operation Jan 23, 2003 Issued
Array ( [id] => 686571 [patent_doc_number] => 07078284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method for forming a notched gate' [patent_app_type] => utility [patent_app_number] => 10/335956 [patent_app_country] => US [patent_app_date] => 2003-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3521 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078284.pdf [firstpage_image] =>[orig_patent_app_number] => 10335956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/335956
Method for forming a notched gate Jan 1, 2003 Issued
Array ( [id] => 6770052 [patent_doc_number] => 20030215992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'METHOD FOR FORMING TRANSISTOR OF SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/331265 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4050 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20030215992.pdf [firstpage_image] =>[orig_patent_app_number] => 10331265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331265
Method for forming transistor of semiconductor device Dec 29, 2002 Issued
Array ( [id] => 7359825 [patent_doc_number] => 20040014281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method of manufacturing flash memory device using trench device isolation process' [patent_app_type] => new [patent_app_number] => 10/329696 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3651 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014281.pdf [firstpage_image] =>[orig_patent_app_number] => 10329696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329696
Method of manufacturing flash memory device using trench device isolation process Dec 26, 2002 Issued
Array ( [id] => 456478 [patent_doc_number] => 07244662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Method for manufacturing semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/322555 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9055 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/244/07244662.pdf [firstpage_image] =>[orig_patent_app_number] => 10322555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322555
Method for manufacturing semiconductor integrated circuit Dec 18, 2002 Issued
Array ( [id] => 6683400 [patent_doc_number] => 20030119264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method for fabricating highly integrated transistor' [patent_app_type] => new [patent_app_number] => 10/323056 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2125 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119264.pdf [firstpage_image] =>[orig_patent_app_number] => 10323056 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323056
Method for fabricating highly integrated transistor Dec 17, 2002 Issued
Array ( [id] => 1046769 [patent_doc_number] => 06864164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'Finfet gate formation using reverse trim of dummy gate' [patent_app_type] => utility [patent_app_number] => 10/320536 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 3215 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864164.pdf [firstpage_image] =>[orig_patent_app_number] => 10320536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/320536
Finfet gate formation using reverse trim of dummy gate Dec 16, 2002 Issued
Array ( [id] => 7359892 [patent_doc_number] => 20040014296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method for forming device isolation layer in semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/316896 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2376 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014296.pdf [firstpage_image] =>[orig_patent_app_number] => 10316896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316896
Method for forming device isolation layer in semiconductor devices Dec 11, 2002 Abandoned
Array ( [id] => 7634777 [patent_doc_number] => 06656841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method of forming multi layer conductive line in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/315126 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3578 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656841.pdf [firstpage_image] =>[orig_patent_app_number] => 10315126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315126
Method of forming multi layer conductive line in semiconductor device Dec 9, 2002 Issued
Array ( [id] => 6765776 [patent_doc_number] => 20030100176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Metal via contact of a semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/314298 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3189 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20030100176.pdf [firstpage_image] =>[orig_patent_app_number] => 10314298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314298
Metal via contact of a semiconductor device and method for fabricating the same Dec 8, 2002 Abandoned
Array ( [id] => 7433456 [patent_doc_number] => 20040002189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Method of forming capacitor in semiconductor device by using a polysilicon pattern in a trapezoid shape' [patent_app_type] => new [patent_app_number] => 10/314296 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1917 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20040002189.pdf [firstpage_image] =>[orig_patent_app_number] => 10314296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314296
Method of forming capacitor in semiconductor device by using a polysilicon pattern in a trapezoid shape Dec 8, 2002 Abandoned
Array ( [id] => 1228254 [patent_doc_number] => 06696348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges' [patent_app_type] => B1 [patent_app_number] => 10/314326 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 3398 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696348.pdf [firstpage_image] =>[orig_patent_app_number] => 10314326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314326
Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges Dec 8, 2002 Issued
Array ( [id] => 1196588 [patent_doc_number] => 06727122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method of fabricating polysilicon thin film transistor' [patent_app_type] => B2 [patent_app_number] => 10/310975 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5611 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727122.pdf [firstpage_image] =>[orig_patent_app_number] => 10310975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310975
Method of fabricating polysilicon thin film transistor Dec 5, 2002 Issued
Array ( [id] => 6683396 [patent_doc_number] => 20030119260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method of manufacturing a flash memory cell' [patent_app_type] => new [patent_app_number] => 10/310746 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3870 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119260.pdf [firstpage_image] =>[orig_patent_app_number] => 10310746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310746
Method of manufacturing a flash memory cell using a self-aligned floating gate Dec 4, 2002 Issued
Array ( [id] => 1273912 [patent_doc_number] => 06649488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method of shallow trench isolation' [patent_app_type] => B2 [patent_app_number] => 10/304696 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2014 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649488.pdf [firstpage_image] =>[orig_patent_app_number] => 10304696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304696
Method of shallow trench isolation Nov 26, 2002 Issued
Array ( [id] => 1192932 [patent_doc_number] => 06730554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Multi-layer silicide block process' [patent_app_type] => B1 [patent_app_number] => 10/301246 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2261 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730554.pdf [firstpage_image] =>[orig_patent_app_number] => 10301246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301246
Multi-layer silicide block process Nov 20, 2002 Issued
Array ( [id] => 1196613 [patent_doc_number] => 06727133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Integrated circuit resistors in a high performance CMOS process' [patent_app_type] => B1 [patent_app_number] => 10/301024 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2121 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727133.pdf [firstpage_image] =>[orig_patent_app_number] => 10301024 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301024
Integrated circuit resistors in a high performance CMOS process Nov 20, 2002 Issued
Array ( [id] => 953853 [patent_doc_number] => 06958267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Methods of forming perovskite-type dielectric materials with chemical vapor deposition' [patent_app_type] => utility [patent_app_number] => 10/302043 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958267.pdf [firstpage_image] =>[orig_patent_app_number] => 10302043 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302043
Methods of forming perovskite-type dielectric materials with chemical vapor deposition Nov 20, 2002 Issued
Array ( [id] => 6801301 [patent_doc_number] => 20030096466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method for forming gate dielectrics of varying thicknesses on a wafer' [patent_app_type] => new [patent_app_number] => 10/301105 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2430 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096466.pdf [firstpage_image] =>[orig_patent_app_number] => 10301105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301105
Method for forming gate dielectrics of varying thicknesses on a wafer Nov 20, 2002 Abandoned
Array ( [id] => 6829956 [patent_doc_number] => 20030181014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method of manufacturing semiconductor device with STI' [patent_app_type] => new [patent_app_number] => 10/293346 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5074 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20030181014.pdf [firstpage_image] =>[orig_patent_app_number] => 10293346 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293346
Method of manufacturing semiconductor device with STI Nov 13, 2002 Abandoned
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