Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7459184 [patent_doc_number] => 20040094782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Use of hafnium silicon oxynitride as the cap layer of the sidewall spacer' [patent_app_type] => new [patent_app_number] => 10/294265 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 765 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094782.pdf [firstpage_image] =>[orig_patent_app_number] => 10294265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/294265
Use of hafnium silicon oxynitride as the cap layer of the sidewall spacer Nov 13, 2002 Abandoned
Array ( [id] => 1228233 [patent_doc_number] => 06696338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method for forming ruthenium storage node of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/291626 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696338.pdf [firstpage_image] =>[orig_patent_app_number] => 10291626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291626
Method for forming ruthenium storage node of semiconductor device Nov 11, 2002 Issued
10/291356 High-k dielectric gate material uniquely formed Nov 7, 2002 Abandoned
Array ( [id] => 1209275 [patent_doc_number] => 06713344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/288455 [patent_app_country] => US [patent_app_date] => 2002-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2726 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713344.pdf [firstpage_image] =>[orig_patent_app_number] => 10288455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288455
Semiconductor device and method for manufacturing the same Nov 5, 2002 Issued
Array ( [id] => 6668982 [patent_doc_number] => 20030113966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/287786 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3866 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113966.pdf [firstpage_image] =>[orig_patent_app_number] => 10287786 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287786
Method of manufacturing semiconductor device having etch stopper for contact hole Nov 4, 2002 Issued
Array ( [id] => 6683393 [patent_doc_number] => 20030119257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method of manufacturing a flash memory cell' [patent_app_type] => new [patent_app_number] => 10/287785 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3376 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119257.pdf [firstpage_image] =>[orig_patent_app_number] => 10287785 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287785
Method of manufacturing a flash memory cell Nov 4, 2002 Abandoned
Array ( [id] => 6680931 [patent_doc_number] => 20030116795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method of manufacturing a tantalum pentaoxide - aluminum oxide film and semiconductor device using the film' [patent_app_type] => new [patent_app_number] => 10/286976 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4453 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20030116795.pdf [firstpage_image] =>[orig_patent_app_number] => 10286976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/286976
Method of manufacturing a tantalum pentaoxide - aluminum oxide film and semiconductor device using the film Nov 3, 2002 Abandoned
Array ( [id] => 1239598 [patent_doc_number] => 06686237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'High precision integrated circuit capacitors' [patent_app_type] => B1 [patent_app_number] => 10/286936 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2027 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686237.pdf [firstpage_image] =>[orig_patent_app_number] => 10286936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/286936
High precision integrated circuit capacitors Oct 30, 2002 Issued
Array ( [id] => 1180812 [patent_doc_number] => 06737302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Manufacturing method for field-effect transistor' [patent_app_type] => B2 [patent_app_number] => 10/284275 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 37 [patent_no_of_words] => 12833 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737302.pdf [firstpage_image] =>[orig_patent_app_number] => 10284275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/284275
Manufacturing method for field-effect transistor Oct 29, 2002 Issued
Array ( [id] => 6870172 [patent_doc_number] => 20030082861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Method for fabricating a MOSFET' [patent_app_type] => new [patent_app_number] => 10/278475 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6603 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082861.pdf [firstpage_image] =>[orig_patent_app_number] => 10278475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278475
Method for fabricating a MOSFET Oct 22, 2002 Issued
Array ( [id] => 7167250 [patent_doc_number] => 20040077142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Atomic layer deposition and plasma treatment method for forming microelectronic capacitor structure with aluminum oxide containing dual dielectric layer' [patent_app_type] => new [patent_app_number] => 10/273046 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4220 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20040077142.pdf [firstpage_image] =>[orig_patent_app_number] => 10273046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273046
Atomic layer deposition and plasma treatment method for forming microelectronic capacitor structure with aluminum oxide containing dual dielectric layer Oct 16, 2002 Abandoned
Array ( [id] => 1277662 [patent_doc_number] => 06645799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method of manufacturing a dual gate semiconductor device with a poly-metal electrode' [patent_app_type] => B2 [patent_app_number] => 10/272369 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5885 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645799.pdf [firstpage_image] =>[orig_patent_app_number] => 10272369 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/272369
Method of manufacturing a dual gate semiconductor device with a poly-metal electrode Oct 16, 2002 Issued
Array ( [id] => 1274166 [patent_doc_number] => 06649538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method for plasma treating and plasma nitriding gate oxides' [patent_app_type] => B1 [patent_app_number] => 10/267955 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3465 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649538.pdf [firstpage_image] =>[orig_patent_app_number] => 10267955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/267955
Method for plasma treating and plasma nitriding gate oxides Oct 8, 2002 Issued
Array ( [id] => 991069 [patent_doc_number] => 06919596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Structure of a capacitive element of a booster circuit included in a semiconductor device and method of manufacturing such a structure' [patent_app_type] => utility [patent_app_number] => 10/267246 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 38 [patent_no_of_words] => 5013 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919596.pdf [firstpage_image] =>[orig_patent_app_number] => 10267246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/267246
Structure of a capacitive element of a booster circuit included in a semiconductor device and method of manufacturing such a structure Oct 8, 2002 Issued
Array ( [id] => 1115643 [patent_doc_number] => 06800550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Method for forming t-shaped conductive wires of semiconductor device utilizing notching phenomenon' [patent_app_type] => B2 [patent_app_number] => 10/265616 [patent_app_country] => US [patent_app_date] => 2002-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2738 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800550.pdf [firstpage_image] =>[orig_patent_app_number] => 10265616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265616
Method for forming t-shaped conductive wires of semiconductor device utilizing notching phenomenon Oct 7, 2002 Issued
10/265955 Memory devices containing a high-K dielectric layer Oct 6, 2002 Abandoned
Array ( [id] => 1288689 [patent_doc_number] => 06632712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method of fabricating variable length vertical transistors' [patent_app_type] => B1 [patent_app_number] => 10/263895 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3369 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 685 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632712.pdf [firstpage_image] =>[orig_patent_app_number] => 10263895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263895
Method of fabricating variable length vertical transistors Oct 2, 2002 Issued
Array ( [id] => 7278788 [patent_doc_number] => 20040061165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component' [patent_app_type] => new [patent_app_number] => 10/262785 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2123 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061165.pdf [firstpage_image] =>[orig_patent_app_number] => 10262785 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262785
Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component Sep 30, 2002 Issued
Array ( [id] => 9216219 [patent_doc_number] => 08629019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Method of forming self aligned contacts for a power MOSFET' [patent_app_type] => utility [patent_app_number] => 10/254385 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5370 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10254385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254385
Method of forming self aligned contacts for a power MOSFET Sep 23, 2002 Issued
Array ( [id] => 7267832 [patent_doc_number] => 20040056350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Electrical connection through nonmetal' [patent_app_type] => new [patent_app_number] => 10/253555 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3336 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20040056350.pdf [firstpage_image] =>[orig_patent_app_number] => 10253555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253555
Electrical connection through nonmetal Sep 23, 2002 Abandoned
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