Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1043656 [patent_doc_number] => 06867089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method of forming a bottle-shaped trench in a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 10/254786 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1876 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867089.pdf [firstpage_image] =>[orig_patent_app_number] => 10254786 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254786
Method of forming a bottle-shaped trench in a semiconductor substrate Sep 23, 2002 Issued
Array ( [id] => 7270005 [patent_doc_number] => 20040058523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Method for forming low dielectric constant damascene structure while employing a carbon doped silicon oxide capping layer' [patent_app_type] => new [patent_app_number] => 10/246895 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058523.pdf [firstpage_image] =>[orig_patent_app_number] => 10246895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246895
Method for forming low dielectric constant damascene structure while employing a carbon doped silicon oxide capping layer Sep 18, 2002 Issued
Array ( [id] => 6718690 [patent_doc_number] => 20030052377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Method of composite gate formation' [patent_app_type] => new [patent_app_number] => 10/236841 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2967 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 39 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20030052377.pdf [firstpage_image] =>[orig_patent_app_number] => 10236841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/236841
Method of composite gate formation Sep 5, 2002 Abandoned
Array ( [id] => 7135189 [patent_doc_number] => 20040043588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method for fabricating n-type carbon nanotube device' [patent_app_type] => new [patent_app_number] => 10/233601 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1739 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043588.pdf [firstpage_image] =>[orig_patent_app_number] => 10233601 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233601
Method for fabricating n-type carbon nanotube device Sep 3, 2002 Issued
Array ( [id] => 7135179 [patent_doc_number] => 20040043583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method of forming nanocrystals in a memory device' [patent_app_type] => new [patent_app_number] => 10/231556 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043583.pdf [firstpage_image] =>[orig_patent_app_number] => 10231556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231556
Method of forming nanocrystals in a memory device Aug 29, 2002 Issued
Array ( [id] => 318595 [patent_doc_number] => 07521304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Method for forming integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/230775 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4943 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/521/07521304.pdf [firstpage_image] =>[orig_patent_app_number] => 10230775 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230775
Method for forming integrated circuit Aug 28, 2002 Issued
Array ( [id] => 6647000 [patent_doc_number] => 20030075766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Methods to form dual metal gates by incorporating metals and their conductive oxides' [patent_app_type] => new [patent_app_number] => 10/227697 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3668 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20030075766.pdf [firstpage_image] =>[orig_patent_app_number] => 10227697 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227697
Methods to form dual metal gates by incorporating metals and their conductive oxides Aug 25, 2002 Issued
Array ( [id] => 6317048 [patent_doc_number] => 20020195672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby' [patent_app_type] => new [patent_app_number] => 10/227343 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20020195672.pdf [firstpage_image] =>[orig_patent_app_number] => 10227343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227343
MOS transistor in a semiconductor device Aug 25, 2002 Issued
Array ( [id] => 1168536 [patent_doc_number] => 06753219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices' [patent_app_type] => B2 [patent_app_number] => 10/226290 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 42 [patent_no_of_words] => 13572 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753219.pdf [firstpage_image] =>[orig_patent_app_number] => 10226290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226290
Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices Aug 22, 2002 Issued
Array ( [id] => 1273869 [patent_doc_number] => 06649479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method for fabricating MOSFET device' [patent_app_type] => B2 [patent_app_number] => 10/226357 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 4014 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649479.pdf [firstpage_image] =>[orig_patent_app_number] => 10226357 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226357
Method for fabricating MOSFET device Aug 22, 2002 Issued
Array ( [id] => 1138289 [patent_doc_number] => 06780731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'HDP gap-filling process for structures with extra step at side-wall' [patent_app_type] => B1 [patent_app_number] => 10/225803 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2727 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780731.pdf [firstpage_image] =>[orig_patent_app_number] => 10225803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225803
HDP gap-filling process for structures with extra step at side-wall Aug 21, 2002 Issued
Array ( [id] => 386632 [patent_doc_number] => 07304001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Fabrication methods of semiconductor integrated circuit device and photomask' [patent_app_type] => utility [patent_app_number] => 10/224375 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 9090 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304001.pdf [firstpage_image] =>[orig_patent_app_number] => 10224375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224375
Fabrication methods of semiconductor integrated circuit device and photomask Aug 20, 2002 Issued
Array ( [id] => 6674356 [patent_doc_number] => 20030059959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method for fabricating capacitor' [patent_app_type] => new [patent_app_number] => 10/224276 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2408 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20030059959.pdf [firstpage_image] =>[orig_patent_app_number] => 10224276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224276
Method for fabricating capacitor Aug 20, 2002 Abandoned
Array ( [id] => 6530393 [patent_doc_number] => 20020192910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Simultaneous formation of charge storage and bitline to wordline isolation' [patent_app_type] => new [patent_app_number] => 10/223195 [patent_app_country] => US [patent_app_date] => 2002-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7730 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192910.pdf [firstpage_image] =>[orig_patent_app_number] => 10223195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223195
Simultaneous formation of charge storage and bitline to wordline isolation Aug 18, 2002 Issued
Array ( [id] => 694733 [patent_doc_number] => 07071043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Methods of forming a field effect transistor having source/drain material over insulative material' [patent_app_type] => utility [patent_app_number] => 10/222326 [patent_app_country] => US [patent_app_date] => 2002-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3720 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071043.pdf [firstpage_image] =>[orig_patent_app_number] => 10222326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222326
Methods of forming a field effect transistor having source/drain material over insulative material Aug 14, 2002 Issued
Array ( [id] => 7313651 [patent_doc_number] => 20040033677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier' [patent_app_type] => new [patent_app_number] => 10/219726 [patent_app_country] => US [patent_app_date] => 2002-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5249 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033677.pdf [firstpage_image] =>[orig_patent_app_number] => 10219726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219726
Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier Aug 13, 2002 Abandoned
Array ( [id] => 296000 [patent_doc_number] => 07541270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Methods for forming openings in doped silicon dioxide' [patent_app_type] => utility [patent_app_number] => 10/218047 [patent_app_country] => US [patent_app_date] => 2002-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2336 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541270.pdf [firstpage_image] =>[orig_patent_app_number] => 10218047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/218047
Methods for forming openings in doped silicon dioxide Aug 12, 2002 Issued
Array ( [id] => 6690873 [patent_doc_number] => 20030038305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method for manufacturing and structure of transistor with low-k spacer' [patent_app_type] => new [patent_app_number] => 10/214667 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3708 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038305.pdf [firstpage_image] =>[orig_patent_app_number] => 10214667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214667
Method for manufacturing and structure of transistor with low-k spacer Aug 7, 2002 Abandoned
Array ( [id] => 1310542 [patent_doc_number] => 06613629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Methods for manufacturing storage nodes of stacked capacitors' [patent_app_type] => B2 [patent_app_number] => 10/213856 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4055 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613629.pdf [firstpage_image] =>[orig_patent_app_number] => 10213856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/213856
Methods for manufacturing storage nodes of stacked capacitors Aug 6, 2002 Issued
Array ( [id] => 7383313 [patent_doc_number] => 20040029321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknesses' [patent_app_type] => new [patent_app_number] => 10/213585 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2464 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029321.pdf [firstpage_image] =>[orig_patent_app_number] => 10213585 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/213585
Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknesses Aug 6, 2002 Abandoned
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