
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6765753
[patent_doc_number] => 20030100153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-29
[patent_title] => 'Method of manufacturing a semiconductor memory, and method of manufacturing a semiconductor device comprising the semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 10/212706
[patent_app_country] => US
[patent_app_date] => 2002-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5593
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20030100153.pdf
[firstpage_image] =>[orig_patent_app_number] => 10212706
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/212706 | Method of manufacturing a semiconductor memory, and method of manufacturing a semiconductor device comprising the semiconductor memory | Aug 6, 2002 | Abandoned |
Array
(
[id] => 6260782
[patent_doc_number] => 20020187654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-12
[patent_title] => 'Methods and apparatus for forming a high dielectric film and the dielectric film formed thereby'
[patent_app_type] => new
[patent_app_number] => 10/213812
[patent_app_country] => US
[patent_app_date] => 2002-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5085
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0187/20020187654.pdf
[firstpage_image] =>[orig_patent_app_number] => 10213812
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/213812 | Methods for forming a high dielectric film | Aug 6, 2002 | Issued |
Array
(
[id] => 7400556
[patent_doc_number] => 20040023454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-05
[patent_title] => 'Method for utilizing re-oxidation of nitride layer to form super thin nitride gate oxide layer'
[patent_app_type] => new
[patent_app_number] => 10/211286
[patent_app_country] => US
[patent_app_date] => 2002-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2030
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20040023454.pdf
[firstpage_image] =>[orig_patent_app_number] => 10211286
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/211286 | Method for utilizing re-oxidation of nitride layer to form super thin nitride gate oxide layer | Aug 4, 2002 | Abandoned |
Array
(
[id] => 6686411
[patent_doc_number] => 20030030134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-13
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/210157
[patent_app_country] => US
[patent_app_date] => 2002-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4994
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20030030134.pdf
[firstpage_image] =>[orig_patent_app_number] => 10210157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/210157 | Semiconductor device | Jul 31, 2002 | Issued |
Array
(
[id] => 6745305
[patent_doc_number] => 20030022488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-30
[patent_title] => 'Method for forming a gate electrode in a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/205987
[patent_app_country] => US
[patent_app_date] => 2002-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7037
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20030022488.pdf
[firstpage_image] =>[orig_patent_app_number] => 10205987
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/205987 | Method for forming a gate electrode in a semiconductor device | Jul 25, 2002 | Issued |
Array
(
[id] => 7398651
[patent_doc_number] => 20040018648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Method for improved metrology of photoresist profiles'
[patent_app_type] => new
[patent_app_number] => 10/202956
[patent_app_country] => US
[patent_app_date] => 2002-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2860
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20040018648.pdf
[firstpage_image] =>[orig_patent_app_number] => 10202956
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/202956 | Method for improved metrology by protecting photoresist profiles | Jul 24, 2002 | Issued |
Array
(
[id] => 749797
[patent_doc_number] => 07022625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-04
[patent_title] => 'Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration'
[patent_app_type] => utility
[patent_app_number] => 10/205517
[patent_app_country] => US
[patent_app_date] => 2002-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1565
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/022/07022625.pdf
[firstpage_image] =>[orig_patent_app_number] => 10205517
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/205517 | Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration | Jul 24, 2002 | Issued |
Array
(
[id] => 6408804
[patent_doc_number] => 20020182813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'Graded LDD implant process for sub-half-micron MOS devices'
[patent_app_type] => new
[patent_app_number] => 10/198941
[patent_app_country] => US
[patent_app_date] => 2002-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2500
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20020182813.pdf
[firstpage_image] =>[orig_patent_app_number] => 10198941
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/198941 | Graded LDD implant process for sub-half-micron MOS devices | Jul 18, 2002 | Issued |
Array
(
[id] => 968838
[patent_doc_number] => 06940115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'Memory cell having a second transistor for holding a charge value'
[patent_app_type] => utility
[patent_app_number] => 10/194877
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2193
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/940/06940115.pdf
[firstpage_image] =>[orig_patent_app_number] => 10194877
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/194877 | Memory cell having a second transistor for holding a charge value | Jul 11, 2002 | Issued |
Array
(
[id] => 7446121
[patent_doc_number] => 20040009651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Method for forming a flash memory by using a microcrystalline polysilicon layer as a floating gate'
[patent_app_type] => new
[patent_app_number] => 10/192565
[patent_app_country] => US
[patent_app_date] => 2002-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3087
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20040009651.pdf
[firstpage_image] =>[orig_patent_app_number] => 10192565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192565 | Method for forming a flash memory by using a microcrystalline polysilicon layer as a floating gate | Jul 10, 2002 | Issued |
Array
(
[id] => 1375731
[patent_doc_number] => 06559013
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Method for fabricating mask ROM device'
[patent_app_type] => B1
[patent_app_number] => 10/064397
[patent_app_country] => US
[patent_app_date] => 2002-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2990
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/559/06559013.pdf
[firstpage_image] =>[orig_patent_app_number] => 10064397
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064397 | Method for fabricating mask ROM device | Jul 9, 2002 | Issued |
Array
(
[id] => 7634376
[patent_doc_number] => 06657244
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation'
[patent_app_type] => B1
[patent_app_number] => 10/195596
[patent_app_country] => US
[patent_app_date] => 2002-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 5113
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/657/06657244.pdf
[firstpage_image] =>[orig_patent_app_number] => 10195596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/195596 | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation | Jun 27, 2002 | Issued |
Array
(
[id] => 6755872
[patent_doc_number] => 20030003649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'Method for forming a capacitor of a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/184706
[patent_app_country] => US
[patent_app_date] => 2002-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1449
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20030003649.pdf
[firstpage_image] =>[orig_patent_app_number] => 10184706
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/184706 | Method for forming a capacitor of a semiconductor device | Jun 27, 2002 | Abandoned |
Array
(
[id] => 1411893
[patent_doc_number] => 06524901
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'Method for forming a notched damascene planar poly/metal gate'
[patent_app_type] => B1
[patent_app_number] => 10/176228
[patent_app_country] => US
[patent_app_date] => 2002-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 3457
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/524/06524901.pdf
[firstpage_image] =>[orig_patent_app_number] => 10176228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/176228 | Method for forming a notched damascene planar poly/metal gate | Jun 19, 2002 | Issued |
Array
(
[id] => 1517236
[patent_doc_number] => 06500712
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Fabrication of dielectric in trenches formed in a semiconductor substrate for a nonvolatile memory'
[patent_app_type] => B1
[patent_app_number] => 10/174442
[patent_app_country] => US
[patent_app_date] => 2002-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1744
[patent_no_of_claims] => 10
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/500/06500712.pdf
[firstpage_image] =>[orig_patent_app_number] => 10174442
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/174442 | Fabrication of dielectric in trenches formed in a semiconductor substrate for a nonvolatile memory | Jun 16, 2002 | Issued |
Array
(
[id] => 6735628
[patent_doc_number] => 20030013263
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-16
[patent_title] => 'Capacitor with high dielectric constant materials and method of making'
[patent_app_type] => new
[patent_app_number] => 10/170987
[patent_app_country] => US
[patent_app_date] => 2002-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3975
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20030013263.pdf
[firstpage_image] =>[orig_patent_app_number] => 10170987
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/170987 | Capacitor with high dielectric constant materials and method of making | Jun 10, 2002 | Abandoned |
Array
(
[id] => 1381651
[patent_doc_number] => 06551877
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Method of manufacturing memory device'
[patent_app_type] => B1
[patent_app_number] => 10/064092
[patent_app_country] => US
[patent_app_date] => 2002-06-11
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/551/06551877.pdf
[firstpage_image] =>[orig_patent_app_number] => 10064092
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064092 | Method of manufacturing memory device | Jun 10, 2002 | Issued |
Array
(
[id] => 6865258
[patent_doc_number] => 20030190784
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'METHOD OF FORMING FLOATING GATE OF FLASH MEMORY'
[patent_app_type] => new
[patent_app_number] => 10/064077
[patent_app_country] => US
[patent_app_date] => 2002-06-10
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20030190784.pdf
[firstpage_image] =>[orig_patent_app_number] => 10064077
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064077 | Method of forming floating gate of flash memory | Jun 9, 2002 | Issued |
Array
(
[id] => 1418087
[patent_doc_number] => 06514821
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'Method for planarizing dielectric layer of flash memory'
[patent_app_type] => B1
[patent_app_number] => 10/165631
[patent_app_country] => US
[patent_app_date] => 2002-06-07
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/514/06514821.pdf
[firstpage_image] =>[orig_patent_app_number] => 10165631
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/165631 | Method for planarizing dielectric layer of flash memory | Jun 6, 2002 | Issued |
Array
(
[id] => 1264497
[patent_doc_number] => 06660621
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation'
[patent_app_type] => B1
[patent_app_number] => 10/163461
[patent_app_country] => US
[patent_app_date] => 2002-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2883
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/660/06660621.pdf
[firstpage_image] =>[orig_patent_app_number] => 10163461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/163461 | Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation | Jun 6, 2002 | Issued |