
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 585068
[patent_doc_number] => 07442610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'Low thermal budget fabrication method for a mask read only memory device'
[patent_app_type] => utility
[patent_app_number] => 10/156323
[patent_app_country] => US
[patent_app_date] => 2002-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1498
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/442/07442610.pdf
[firstpage_image] =>[orig_patent_app_number] => 10156323
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/156323 | Low thermal budget fabrication method for a mask read only memory device | May 23, 2002 | Issued |
Array
(
[id] => 6447272
[patent_doc_number] => 20020177284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Method of using sacrificial spacers to reduce short channel effect'
[patent_app_type] => new
[patent_app_number] => 10/154281
[patent_app_country] => US
[patent_app_date] => 2002-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1602
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20020177284.pdf
[firstpage_image] =>[orig_patent_app_number] => 10154281
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/154281 | Method of using sacrificial spacers to reduce short channel effect | May 22, 2002 | Abandoned |
Array
(
[id] => 1440062
[patent_doc_number] => 06495430
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Process for fabricating sharp corner-free shallow trench isolation structure'
[patent_app_type] => B1
[patent_app_number] => 10/151112
[patent_app_country] => US
[patent_app_date] => 2002-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 1885
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/495/06495430.pdf
[firstpage_image] =>[orig_patent_app_number] => 10151112
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/151112 | Process for fabricating sharp corner-free shallow trench isolation structure | May 20, 2002 | Issued |
Array
(
[id] => 1395610
[patent_doc_number] => 06548855
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Non-volatile memory dielectric as charge pump dielectric'
[patent_app_type] => B1
[patent_app_number] => 10/147622
[patent_app_country] => US
[patent_app_date] => 2002-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 4155
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/548/06548855.pdf
[firstpage_image] =>[orig_patent_app_number] => 10147622
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/147622 | Non-volatile memory dielectric as charge pump dielectric | May 15, 2002 | Issued |
Array
(
[id] => 1534502
[patent_doc_number] => 06489191
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-03
[patent_title] => 'Method for forming self-aligned channel implants using a gate poly reverse mask'
[patent_app_type] => B2
[patent_app_number] => 10/140571
[patent_app_country] => US
[patent_app_date] => 2002-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3145
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489191.pdf
[firstpage_image] =>[orig_patent_app_number] => 10140571
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/140571 | Method for forming self-aligned channel implants using a gate poly reverse mask | May 7, 2002 | Issued |
Array
(
[id] => 5859262
[patent_doc_number] => 20020123190
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-05
[patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/137426
[patent_app_country] => US
[patent_app_date] => 2002-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 49
[patent_figures_cnt] => 49
[patent_no_of_words] => 25476
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0123/20020123190.pdf
[firstpage_image] =>[orig_patent_app_number] => 10137426
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137426 | Dynamic random access memory with improved contact arrangements | May 2, 2002 | Issued |
Array
(
[id] => 5787422
[patent_doc_number] => 20020160572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'High voltage device and method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/132407
[patent_app_country] => US
[patent_app_date] => 2002-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2910
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20020160572.pdf
[firstpage_image] =>[orig_patent_app_number] => 10132407
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/132407 | Method for fabricating a high voltage device | Apr 25, 2002 | Issued |
Array
(
[id] => 817059
[patent_doc_number] => 07410867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-12
[patent_title] => 'Vertical transistor with horizontal gate layers'
[patent_app_type] => utility
[patent_app_number] => 10/124019
[patent_app_country] => US
[patent_app_date] => 2002-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 25
[patent_no_of_words] => 10126
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/410/07410867.pdf
[firstpage_image] =>[orig_patent_app_number] => 10124019
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/124019 | Vertical transistor with horizontal gate layers | Apr 15, 2002 | Issued |
Array
(
[id] => 6111313
[patent_doc_number] => 20020173096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Semiconductor integrated circuit and method of manufacturing same'
[patent_app_type] => new
[patent_app_number] => 10/109837
[patent_app_country] => US
[patent_app_date] => 2002-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 12227
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20020173096.pdf
[firstpage_image] =>[orig_patent_app_number] => 10109837
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/109837 | Semiconductor integrated circuit and method of manufacturing same | Mar 31, 2002 | Abandoned |
Array
(
[id] => 5986404
[patent_doc_number] => 20020098663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-25
[patent_title] => 'Manufacturing method of a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/106063
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5849
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20020098663.pdf
[firstpage_image] =>[orig_patent_app_number] => 10106063
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/106063 | Manufacturing method of a semiconductor device | Mar 26, 2002 | Abandoned |
Array
(
[id] => 7645700
[patent_doc_number] => 06472269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-29
[patent_title] => 'Method for forming capacitor'
[patent_app_type] => B2
[patent_app_number] => 10/096962
[patent_app_country] => US
[patent_app_date] => 2002-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2969
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/472/06472269.pdf
[firstpage_image] =>[orig_patent_app_number] => 10096962
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/096962 | Method for forming capacitor | Mar 13, 2002 | Issued |
Array
(
[id] => 1449990
[patent_doc_number] => 06455388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method of manufacturing metal-oxide semiconductor transistor'
[patent_app_type] => B1
[patent_app_number] => 10/099802
[patent_app_country] => US
[patent_app_date] => 2002-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1534
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455388.pdf
[firstpage_image] =>[orig_patent_app_number] => 10099802
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/099802 | Method of manufacturing metal-oxide semiconductor transistor | Mar 12, 2002 | Issued |
Array
(
[id] => 1256036
[patent_doc_number] => 06667199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-23
[patent_title] => 'Semiconductor device having a replacement gate type field effect transistor and its manufacturing method'
[patent_app_type] => B2
[patent_app_number] => 10/081227
[patent_app_country] => US
[patent_app_date] => 2002-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 26
[patent_no_of_words] => 10160
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/667/06667199.pdf
[firstpage_image] =>[orig_patent_app_number] => 10081227
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/081227 | Semiconductor device having a replacement gate type field effect transistor and its manufacturing method | Feb 24, 2002 | Issued |
Array
(
[id] => 1172508
[patent_doc_number] => 06750096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-15
[patent_title] => 'Trench capacitor with buried plate and method for its production'
[patent_app_type] => B2
[patent_app_number] => 10/078997
[patent_app_country] => US
[patent_app_date] => 2002-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3056
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/750/06750096.pdf
[firstpage_image] =>[orig_patent_app_number] => 10078997
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/078997 | Trench capacitor with buried plate and method for its production | Feb 19, 2002 | Issued |
Array
(
[id] => 6783113
[patent_doc_number] => 20030064560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/075277
[patent_app_country] => US
[patent_app_date] => 2002-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4628
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20030064560.pdf
[firstpage_image] =>[orig_patent_app_number] => 10075277
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/075277 | Method for manufacturing a lateral double-diffused MOS transistor having stable characteristics and equal drift length | Feb 14, 2002 | Issued |
Array
(
[id] => 1241154
[patent_doc_number] => 06682977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-27
[patent_title] => 'Method for fabricating a gate structure of a flash memory'
[patent_app_type] => B2
[patent_app_number] => 10/071187
[patent_app_country] => US
[patent_app_date] => 2002-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2283
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/682/06682977.pdf
[firstpage_image] =>[orig_patent_app_number] => 10071187
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/071187 | Method for fabricating a gate structure of a flash memory | Feb 10, 2002 | Issued |
Array
(
[id] => 1590772
[patent_doc_number] => 06483148
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-19
[patent_title] => 'Self-aligned elevated transistor'
[patent_app_type] => B2
[patent_app_number] => 10/060818
[patent_app_country] => US
[patent_app_date] => 2002-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 2719
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/483/06483148.pdf
[firstpage_image] =>[orig_patent_app_number] => 10060818
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/060818 | Self-aligned elevated transistor | Jan 31, 2002 | Issued |
Array
(
[id] => 5986348
[patent_doc_number] => 20020098652
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-25
[patent_title] => 'Semiconductor device having MISFETs'
[patent_app_type] => new
[patent_app_number] => 10/060297
[patent_app_country] => US
[patent_app_date] => 2002-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 24361
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20020098652.pdf
[firstpage_image] =>[orig_patent_app_number] => 10060297
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/060297 | Semiconductor device having MISFETs | Jan 31, 2002 | Abandoned |
Array
(
[id] => 6843227
[patent_doc_number] => 20030148574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Method for making an integrated circuit device including photodiodes'
[patent_app_type] => new
[patent_app_number] => 10/061857
[patent_app_country] => US
[patent_app_date] => 2002-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5803
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20030148574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10061857
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/061857 | Method for making an integrated circuit device including photodiodes | Jan 31, 2002 | Issued |
Array
(
[id] => 1534517
[patent_doc_number] => 06489196
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Method of forming a capacitor with high capacitance and low voltage coefficient'
[patent_app_type] => B1
[patent_app_number] => 10/055943
[patent_app_country] => US
[patent_app_date] => 2002-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1600
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489196.pdf
[firstpage_image] =>[orig_patent_app_number] => 10055943
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055943 | Method of forming a capacitor with high capacitance and low voltage coefficient | Jan 27, 2002 | Issued |