Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1119651 [patent_doc_number] => 06797558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer' [patent_app_type] => B2 [patent_app_number] => 10/050426 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3625 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797558.pdf [firstpage_image] =>[orig_patent_app_number] => 10050426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050426
Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer Jan 14, 2002 Issued
Array ( [id] => 1302848 [patent_doc_number] => 06620684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method of manufacturing nonvolatile memory cell' [patent_app_type] => B2 [patent_app_number] => 10/029391 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 4091 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620684.pdf [firstpage_image] =>[orig_patent_app_number] => 10029391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029391
Method of manufacturing nonvolatile memory cell Dec 27, 2001 Issued
Array ( [id] => 1600422 [patent_doc_number] => 06475886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Fabrication method of nanocrystals using a focused-ion beam' [patent_app_type] => B2 [patent_app_number] => 10/025696 [patent_app_country] => US [patent_app_date] => 2001-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1342 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475886.pdf [firstpage_image] =>[orig_patent_app_number] => 10025696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025696
Fabrication method of nanocrystals using a focused-ion beam Dec 25, 2001 Issued
Array ( [id] => 557435 [patent_doc_number] => 07157359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Method of forming a metal gate in a semiconductor device using atomic layer deposition process' [patent_app_type] => utility [patent_app_number] => 10/036156 [patent_app_country] => US [patent_app_date] => 2001-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2766 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157359.pdf [firstpage_image] =>[orig_patent_app_number] => 10036156 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036156
Method of forming a metal gate in a semiconductor device using atomic layer deposition process Dec 25, 2001 Issued
Array ( [id] => 557270 [patent_doc_number] => 07157344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Vapor-phase growth method, semiconductor manufacturing method and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/204386 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8578 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157344.pdf [firstpage_image] =>[orig_patent_app_number] => 10204386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/204386
Vapor-phase growth method, semiconductor manufacturing method and semiconductor device manufacturing method Dec 19, 2001 Issued
Array ( [id] => 953887 [patent_doc_number] => 06958301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Method for forming Ta2O5 dielectric layer by using in situ N2O plasma treatment' [patent_app_type] => utility [patent_app_number] => 10/013528 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1525 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958301.pdf [firstpage_image] =>[orig_patent_app_number] => 10013528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013528
Method for forming Ta2O5 dielectric layer by using in situ N2O plasma treatment Dec 12, 2001 Issued
Array ( [id] => 1245663 [patent_doc_number] => 06677189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method for forming polysilicon thin film transistor with a self-aligned LDD structure' [patent_app_type] => B2 [patent_app_number] => 10/008848 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1579 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677189.pdf [firstpage_image] =>[orig_patent_app_number] => 10008848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008848
Method for forming polysilicon thin film transistor with a self-aligned LDD structure Nov 29, 2001 Issued
Array ( [id] => 7963835 [patent_doc_number] => 06680510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Non-volatile memory device having a cell transistor and a non-cell transistor' [patent_app_type] => B2 [patent_app_number] => 09/996753 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4639 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680510.pdf [firstpage_image] =>[orig_patent_app_number] => 09996753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996753
Non-volatile memory device having a cell transistor and a non-cell transistor Nov 29, 2001 Issued
Array ( [id] => 6290341 [patent_doc_number] => 20020055206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor' [patent_app_type] => new [patent_app_number] => 09/987607 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4970 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055206.pdf [firstpage_image] =>[orig_patent_app_number] => 09987607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987607
Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor Nov 14, 2001 Issued
Array ( [id] => 1063651 [patent_doc_number] => 06849896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Flash memory with UV opaque passivation layer' [patent_app_type] => utility [patent_app_number] => 10/052853 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1858 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849896.pdf [firstpage_image] =>[orig_patent_app_number] => 10052853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052853
Flash memory with UV opaque passivation layer Nov 8, 2001 Issued
Array ( [id] => 6867700 [patent_doc_number] => 20030080389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Semiconductor device having a dielectric layer with a uniform nitrogen profile' [patent_app_type] => new [patent_app_number] => 10/001338 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3342 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20030080389.pdf [firstpage_image] =>[orig_patent_app_number] => 10001338 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001338
Semiconductor device having a dielectric layer with a uniform nitrogen profile Oct 30, 2001 Abandoned
Array ( [id] => 6595205 [patent_doc_number] => 20020042183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Two-step MOSFET gate formation for high-density devices' [patent_app_type] => new [patent_app_number] => 09/983394 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5026 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20020042183.pdf [firstpage_image] =>[orig_patent_app_number] => 09983394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983394
Two-step MOSFET gate formation for high-density devices Oct 23, 2001 Abandoned
Array ( [id] => 1449982 [patent_doc_number] => 06455384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers' [patent_app_type] => B2 [patent_app_number] => 09/972645 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3744 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455384.pdf [firstpage_image] =>[orig_patent_app_number] => 09972645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972645
Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers Oct 8, 2001 Issued
Array ( [id] => 1123335 [patent_doc_number] => 06794239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method of fabrication of semiconductor structures by ion implantation' [patent_app_type] => B2 [patent_app_number] => 09/952890 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794239.pdf [firstpage_image] =>[orig_patent_app_number] => 09952890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952890
Method of fabrication of semiconductor structures by ion implantation Sep 13, 2001 Issued
Array ( [id] => 5951492 [patent_doc_number] => 20020006715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Method for forming an extended metal gate using a damascene process' [patent_app_type] => new [patent_app_number] => 09/946982 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4074 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006715.pdf [firstpage_image] =>[orig_patent_app_number] => 09946982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946982
Method for forming an extended metal gate using a damascene process Sep 5, 2001 Issued
Array ( [id] => 6284980 [patent_doc_number] => 20020053708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Non-volatile memory device used for non-overlapping implant and device fabricating method' [patent_app_type] => new [patent_app_number] => 09/939982 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2162 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053708.pdf [firstpage_image] =>[orig_patent_app_number] => 09939982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939982
Non-volatile memory device used for non-overlapping implant Aug 22, 2001 Issued
Array ( [id] => 6692739 [patent_doc_number] => 20030040171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method of composite gate formation' [patent_app_type] => new [patent_app_number] => 09/935255 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2967 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 39 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040171.pdf [firstpage_image] =>[orig_patent_app_number] => 09935255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935255
Method of composite gate formation Aug 21, 2001 Abandoned
Array ( [id] => 6277148 [patent_doc_number] => 20020106863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Method for fabricating semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/934179 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1457 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106863.pdf [firstpage_image] =>[orig_patent_app_number] => 09934179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934179
Method for fabricating semiconductor devices Aug 20, 2001 Abandoned
Array ( [id] => 1134083 [patent_doc_number] => 06784038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Process for producing semiconductor integrated circuit device and semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/929091 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 12076 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784038.pdf [firstpage_image] =>[orig_patent_app_number] => 09929091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929091
Process for producing semiconductor integrated circuit device and semiconductor integrated circuit device Aug 14, 2001 Issued
Array ( [id] => 6000057 [patent_doc_number] => 20020028569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Semiconductor device and method of manufacturing same' [patent_app_type] => new [patent_app_number] => 09/927635 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028569.pdf [firstpage_image] =>[orig_patent_app_number] => 09927635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927635
Method for forming a semiconductor device having a plurality of circuits parts Aug 12, 2001 Issued
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