
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6427371
[patent_doc_number] => 20020175371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Device improvement by lowering LDD resistance with new silicide process'
[patent_app_type] => new
[patent_app_number] => 10/195566
[patent_app_country] => US
[patent_app_date] => 2001-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5506
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20020175371.pdf
[firstpage_image] =>[orig_patent_app_number] => 10195566
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/195566 | Device improvement by lowering LDD resistance with new silicide process | Apr 15, 2001 | Abandoned |
Array
(
[id] => 6880259
[patent_doc_number] => 20010031546
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-18
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/829795
[patent_app_country] => US
[patent_app_date] => 2001-04-10
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2154
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20010031546.pdf
[firstpage_image] =>[orig_patent_app_number] => 09829795
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/829795 | Method of manufacturing a semiconductor device | Apr 9, 2001 | Abandoned |
Array
(
[id] => 1462454
[patent_doc_number] => 06350639
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Simplified graded LDD transistor using controlled polysilicon gate profile'
[patent_app_type] => B1
[patent_app_number] => 09/832684
[patent_app_country] => US
[patent_app_date] => 2001-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[patent_no_of_words] => 12252
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350639.pdf
[firstpage_image] =>[orig_patent_app_number] => 09832684
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/832684 | Simplified graded LDD transistor using controlled polysilicon gate profile | Apr 9, 2001 | Issued |
Array
(
[id] => 1278092
[patent_doc_number] => 06645875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Method of processing metal and method of manufacturing semiconductor device using the metal'
[patent_app_type] => B2
[patent_app_number] => 09/824726
[patent_app_country] => US
[patent_app_date] => 2001-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4447
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/645/06645875.pdf
[firstpage_image] =>[orig_patent_app_number] => 09824726
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/824726 | Method of processing metal and method of manufacturing semiconductor device using the metal | Apr 3, 2001 | Issued |
Array
(
[id] => 6934523
[patent_doc_number] => 20010055867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-27
[patent_title] => 'Method of forming self-aligned contacts in a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/825346
[patent_app_country] => US
[patent_app_date] => 2001-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4229
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20010055867.pdf
[firstpage_image] =>[orig_patent_app_number] => 09825346
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/825346 | Method of forming self-aligned contacts in a semiconductor device | Apr 3, 2001 | Issued |
Array
(
[id] => 6616470
[patent_doc_number] => 20020016035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4 layer across the substrate'
[patent_app_type] => new
[patent_app_number] => 09/816356
[patent_app_country] => US
[patent_app_date] => 2001-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 4616
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[pdf_file] => publications/A1/0016/20020016035.pdf
[firstpage_image] =>[orig_patent_app_number] => 09816356
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/816356 | Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate | Mar 25, 2001 | Issued |
Array
(
[id] => 5844551
[patent_doc_number] => 20020132431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'METHOD FOR FORMING NOTCH GATE HAVING SELF-ALIGNED RAISED SOURCE/DRAIN STRUCTURE'
[patent_app_type] => new
[patent_app_number] => 09/811706
[patent_app_country] => US
[patent_app_date] => 2001-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2245
[patent_no_of_claims] => 13
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[pdf_file] => publications/A1/0132/20020132431.pdf
[firstpage_image] =>[orig_patent_app_number] => 09811706
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/811706 | Method for forming notch gate having self-aligned raised source/drain structure | Mar 18, 2001 | Issued |
Array
(
[id] => 5844587
[patent_doc_number] => 20020132457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'Method for avoiding the ion penetration with the plasma doping'
[patent_app_type] => new
[patent_app_number] => 09/803986
[patent_app_country] => US
[patent_app_date] => 2001-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3387
[patent_no_of_claims] => 32
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[pdf_file] => publications/A1/0132/20020132457.pdf
[firstpage_image] =>[orig_patent_app_number] => 09803986
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/803986 | Method for avoiding the ion penetration with the plasma doping | Mar 12, 2001 | Abandoned |
Array
(
[id] => 1602601
[patent_doc_number] => 06432780
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Method for suppressing boron penetrating gate dielectric layer by pulsed nitrogen plasma doping'
[patent_app_type] => B1
[patent_app_number] => 09/795936
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/432/06432780.pdf
[firstpage_image] =>[orig_patent_app_number] => 09795936
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795936 | Method for suppressing boron penetrating gate dielectric layer by pulsed nitrogen plasma doping | Feb 27, 2001 | Issued |
Array
(
[id] => 4326743
[patent_doc_number] => 06319781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Method of fabricating self-aligned multilevel mask ROM'
[patent_app_type] => 1
[patent_app_number] => 9/794146
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2408
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[pdf_file] => patents/06/319/06319781.pdf
[firstpage_image] =>[orig_patent_app_number] => 794146
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/794146 | Method of fabricating self-aligned multilevel mask ROM | Feb 27, 2001 | Issued |
Array
(
[id] => 1600358
[patent_doc_number] => 06475869
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Method of forming a double gate transistor having an epitaxial silicon/germanium channel region'
[patent_app_type] => B1
[patent_app_number] => 09/793055
[patent_app_country] => US
[patent_app_date] => 2001-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/475/06475869.pdf
[firstpage_image] =>[orig_patent_app_number] => 09793055
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/793055 | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region | Feb 25, 2001 | Issued |
Array
(
[id] => 1396379
[patent_doc_number] => 06531349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-11
[patent_title] => 'Method of etching polycrystalline silicon film by using two consecutive dry-etching processes'
[patent_app_type] => B2
[patent_app_number] => 09/790075
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[patent_app_date] => 2001-02-21
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[firstpage_image] =>[orig_patent_app_number] => 09790075
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790075 | Method of etching polycrystalline silicon film by using two consecutive dry-etching processes | Feb 20, 2001 | Issued |
Array
(
[id] => 1459373
[patent_doc_number] => 06391718
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Planarization method for flash memory device'
[patent_app_type] => B1
[patent_app_number] => 09/788705
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/788705 | Planarization method for flash memory device | Feb 19, 2001 | Issued |
Array
(
[id] => 1507393
[patent_doc_number] => 06440826
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[patent_issue_date] => 2002-08-27
[patent_title] => 'NiSi contacting extensions of active regions'
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[patent_app_number] => 09/785176
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/785176 | NiSi contacting extensions of active regions | Feb 19, 2001 | Issued |
Array
(
[id] => 1528068
[patent_doc_number] => 06479355
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[patent_kind] => B2
[patent_issue_date] => 2002-11-12
[patent_title] => 'Method for forming landing pad'
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[patent_app_number] => 09/784235
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[firstpage_image] =>[orig_patent_app_number] => 09784235
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/784235 | Method for forming landing pad | Feb 12, 2001 | Issued |
Array
(
[id] => 1585439
[patent_doc_number] => 06358797
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[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Method of forming a non-volatile memory cell'
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[patent_app_number] => 09/782266
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[firstpage_image] =>[orig_patent_app_number] => 09782266
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/782266 | Method of forming a non-volatile memory cell | Feb 11, 2001 | Issued |
Array
(
[id] => 1165337
[patent_doc_number] => 06756277
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-29
[patent_title] => 'Replacement gate process for transistors having elevated source and drain regions'
[patent_app_type] => B1
[patent_app_number] => 09/779985
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Array
(
[id] => 6547735
[patent_doc_number] => 20020110979
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[patent_kind] => A1
[patent_issue_date] => 2002-08-15
[patent_title] => 'METHOD FOR FORMING A DRAM CONTACT PLUG'
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[firstpage_image] =>[orig_patent_app_number] => 09779485
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/779485 | METHOD FOR FORMING A DRAM CONTACT PLUG | Feb 8, 2001 | Abandoned |
Array
(
[id] => 1059506
[patent_doc_number] => 06852596
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[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Electronic memory circuit and related manufacturing method'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/779956 | Electronic memory circuit and related manufacturing method | Feb 8, 2001 | Issued |
Array
(
[id] => 4404760
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[patent_title] => 'Method for fabricating a semiconductor device'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/271/06271092.pdf
[firstpage_image] =>[orig_patent_app_number] => 770305
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/770305 | Method for fabricating a semiconductor device | Jan 28, 2001 | Issued |