
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1565694
[patent_doc_number] => 06376294
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process'
[patent_app_type] => B1
[patent_app_number] => 09/755686
[patent_app_country] => US
[patent_app_date] => 2001-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2611
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/376/06376294.pdf
[firstpage_image] =>[orig_patent_app_number] => 09755686
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/755686 | Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process | Jan 7, 2001 | Issued |
Array
(
[id] => 4303689
[patent_doc_number] => 06326261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Method of fabricating a deep trench capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/754345
[patent_app_country] => US
[patent_app_date] => 2001-01-05
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2757
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/326/06326261.pdf
[firstpage_image] =>[orig_patent_app_number] => 754345
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/754345 | Method of fabricating a deep trench capacitor | Jan 4, 2001 | Issued |
Array
(
[id] => 196567
[patent_doc_number] => 07638380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Method for manufacturing a laterally diffused metal oxide semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 09/755828
[patent_app_country] => US
[patent_app_date] => 2001-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/07/638/07638380.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/755828 | Method for manufacturing a laterally diffused metal oxide semiconductor device | Jan 3, 2001 | Issued |
Array
(
[id] => 4441874
[patent_doc_number] => 07927939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Method of manufacturing a laterally diffused metal oxide semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 09/755826
[patent_app_country] => US
[patent_app_date] => 2001-01-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/927/07927939.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/755826 | Method of manufacturing a laterally diffused metal oxide semiconductor device | Jan 3, 2001 | Issued |
Array
(
[id] => 5859358
[patent_doc_number] => 20020123226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-05
[patent_title] => 'Method and composition for plasma etching of a self-aligned contact opening'
[patent_app_type] => new
[patent_app_number] => 09/752685
[patent_app_country] => US
[patent_app_date] => 2001-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0123/20020123226.pdf
[firstpage_image] =>[orig_patent_app_number] => 09752685
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/752685 | Method for forming a contact opening in a semiconductor device | Jan 2, 2001 | Issued |
Array
(
[id] => 6876690
[patent_doc_number] => 20010006843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-05
[patent_title] => 'Method for forming a gate insulating film for semiconductor devices'
[patent_app_type] => new-utility
[patent_app_number] => 09/750226
[patent_app_country] => US
[patent_app_date] => 2000-12-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0006/20010006843.pdf
[firstpage_image] =>[orig_patent_app_number] => 09750226
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/750226 | Method for forming a gate insulating film for semiconductor devices | Dec 28, 2000 | Issued |
Array
(
[id] => 7041015
[patent_doc_number] => 20010005612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-06-28
[patent_title] => 'METHOD FOR FORMING A CAPACITOR USING TANTALUM NITRIDE AS A CAPACITOR DIELECTRIC'
[patent_app_type] => new-utility
[patent_app_number] => 09/741875
[patent_app_country] => US
[patent_app_date] => 2000-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3164
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[pdf_file] => publications/A1/0005/20010005612.pdf
[firstpage_image] =>[orig_patent_app_number] => 09741875
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741875 | Method for forming a capacitor using tantalum nitride as a capacitor dielectric | Dec 21, 2000 | Issued |
Array
(
[id] => 6901519
[patent_doc_number] => 20010023102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-20
[patent_title] => 'Semiconductor memory device using hemispherical grain silicon and method for the manufacture thereof'
[patent_app_type] => new
[patent_app_number] => 09/739886
[patent_app_country] => US
[patent_app_date] => 2000-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2327
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[pdf_file] => publications/A1/0023/20010023102.pdf
[firstpage_image] =>[orig_patent_app_number] => 09739886
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739886 | Semiconductor memory device using hemispherical grain silicon for bottom electrodes | Dec 19, 2000 | Issued |
Array
(
[id] => 1578077
[patent_doc_number] => 06448127
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets'
[patent_app_type] => B1
[patent_app_number] => 09/740606
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/448/06448127.pdf
[firstpage_image] =>[orig_patent_app_number] => 09740606
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/740606 | Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets | Dec 18, 2000 | Issued |
Array
(
[id] => 1595475
[patent_doc_number] => 06492222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices'
[patent_app_type] => B1
[patent_app_number] => 09/739065
[patent_app_country] => US
[patent_app_date] => 2000-12-18
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09739065
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739065 | Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices | Dec 17, 2000 | Issued |
Array
(
[id] => 4408270
[patent_doc_number] => 06300196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-09
[patent_title] => 'Method of fabricating gate'
[patent_app_type] => 1
[patent_app_number] => 9/734406
[patent_app_country] => US
[patent_app_date] => 2000-12-11
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Array
(
[id] => 4368692
[patent_doc_number] => 06287916
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[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss'
[patent_app_type] => 1
[patent_app_number] => 9/731185
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Array
(
[id] => 1469760
[patent_doc_number] => 06406950
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[patent_issue_date] => 2002-06-18
[patent_title] => 'Definition of small damascene metal gates using reverse through approach'
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Array
(
[id] => 1193004
[patent_doc_number] => 06730587
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[patent_issue_date] => 2004-05-04
[patent_title] => 'Titanium barrier for nickel silicidation of a gate electrode'
[patent_app_type] => B1
[patent_app_number] => 09/731006
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Array
(
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[patent_title] => 'Simultaneous formation of charge storage and bitline to wordline isolation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/723635 | Simultaneous formation of charge storage and bitline to wordline isolation | Nov 27, 2000 | Issued |
Array
(
[id] => 1435905
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[patent_issue_date] => 2002-03-12
[patent_title] => 'Method for manufacturing a gate structure incorporated therein a high K dielectric'
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[patent_app_number] => 09/722465
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Array
(
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[patent_title] => 'Method of forming a gate electrode in a semiconductor device'
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715826 | Method for fabricating semiconductor devices with dual gate oxides | Nov 16, 2000 | Issued |
Array
(
[id] => 1441012
[patent_doc_number] => 06495889
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[patent_title] => 'Semiconductor device having self-aligned contacts'
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[firstpage_image] =>[orig_patent_app_number] => 09713025
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/713025 | Semiconductor device having self-aligned contacts | Nov 15, 2000 | Issued |