Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1565694 [patent_doc_number] => 06376294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process' [patent_app_type] => B1 [patent_app_number] => 09/755686 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2611 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376294.pdf [firstpage_image] =>[orig_patent_app_number] => 09755686 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755686
Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process Jan 7, 2001 Issued
Array ( [id] => 4303689 [patent_doc_number] => 06326261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method of fabricating a deep trench capacitor' [patent_app_type] => 1 [patent_app_number] => 9/754345 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2757 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326261.pdf [firstpage_image] =>[orig_patent_app_number] => 754345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754345
Method of fabricating a deep trench capacitor Jan 4, 2001 Issued
Array ( [id] => 196567 [patent_doc_number] => 07638380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method for manufacturing a laterally diffused metal oxide semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/755828 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/638/07638380.pdf [firstpage_image] =>[orig_patent_app_number] => 09755828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755828
Method for manufacturing a laterally diffused metal oxide semiconductor device Jan 3, 2001 Issued
Array ( [id] => 4441874 [patent_doc_number] => 07927939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method of manufacturing a laterally diffused metal oxide semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/755826 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2332 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/927/07927939.pdf [firstpage_image] =>[orig_patent_app_number] => 09755826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755826
Method of manufacturing a laterally diffused metal oxide semiconductor device Jan 3, 2001 Issued
Array ( [id] => 5859358 [patent_doc_number] => 20020123226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Method and composition for plasma etching of a self-aligned contact opening' [patent_app_type] => new [patent_app_number] => 09/752685 [patent_app_country] => US [patent_app_date] => 2001-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3234 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20020123226.pdf [firstpage_image] =>[orig_patent_app_number] => 09752685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752685
Method for forming a contact opening in a semiconductor device Jan 2, 2001 Issued
Array ( [id] => 6876690 [patent_doc_number] => 20010006843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Method for forming a gate insulating film for semiconductor devices' [patent_app_type] => new-utility [patent_app_number] => 09/750226 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2540 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006843.pdf [firstpage_image] =>[orig_patent_app_number] => 09750226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750226
Method for forming a gate insulating film for semiconductor devices Dec 28, 2000 Issued
Array ( [id] => 7041015 [patent_doc_number] => 20010005612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'METHOD FOR FORMING A CAPACITOR USING TANTALUM NITRIDE AS A CAPACITOR DIELECTRIC' [patent_app_type] => new-utility [patent_app_number] => 09/741875 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005612.pdf [firstpage_image] =>[orig_patent_app_number] => 09741875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741875
Method for forming a capacitor using tantalum nitride as a capacitor dielectric Dec 21, 2000 Issued
Array ( [id] => 6901519 [patent_doc_number] => 20010023102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Semiconductor memory device using hemispherical grain silicon and method for the manufacture thereof' [patent_app_type] => new [patent_app_number] => 09/739886 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023102.pdf [firstpage_image] =>[orig_patent_app_number] => 09739886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739886
Semiconductor memory device using hemispherical grain silicon for bottom electrodes Dec 19, 2000 Issued
Array ( [id] => 1578077 [patent_doc_number] => 06448127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets' [patent_app_type] => B1 [patent_app_number] => 09/740606 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1061 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448127.pdf [firstpage_image] =>[orig_patent_app_number] => 09740606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740606
Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets Dec 18, 2000 Issued
Array ( [id] => 1595475 [patent_doc_number] => 06492222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices' [patent_app_type] => B1 [patent_app_number] => 09/739065 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 15468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492222.pdf [firstpage_image] =>[orig_patent_app_number] => 09739065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739065
Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices Dec 17, 2000 Issued
Array ( [id] => 4408270 [patent_doc_number] => 06300196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method of fabricating gate' [patent_app_type] => 1 [patent_app_number] => 9/734406 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4830 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300196.pdf [firstpage_image] =>[orig_patent_app_number] => 734406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734406
Method of fabricating gate Dec 10, 2000 Issued
Array ( [id] => 4368692 [patent_doc_number] => 06287916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss' [patent_app_type] => 1 [patent_app_number] => 9/731185 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1951 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287916.pdf [firstpage_image] =>[orig_patent_app_number] => 731185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731185
Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss Dec 6, 2000 Issued
Array ( [id] => 1469760 [patent_doc_number] => 06406950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Definition of small damascene metal gates using reverse through approach' [patent_app_type] => B1 [patent_app_number] => 09/732125 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4198 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406950.pdf [firstpage_image] =>[orig_patent_app_number] => 09732125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/732125
Definition of small damascene metal gates using reverse through approach Dec 6, 2000 Issued
Array ( [id] => 1193004 [patent_doc_number] => 06730587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Titanium barrier for nickel silicidation of a gate electrode' [patent_app_type] => B1 [patent_app_number] => 09/731006 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2608 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730587.pdf [firstpage_image] =>[orig_patent_app_number] => 09731006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731006
Titanium barrier for nickel silicidation of a gate electrode Dec 6, 2000 Issued
Array ( [id] => 1503461 [patent_doc_number] => 06465306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Simultaneous formation of charge storage and bitline to wordline isolation' [patent_app_type] => B1 [patent_app_number] => 09/723635 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7715 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465306.pdf [firstpage_image] =>[orig_patent_app_number] => 09723635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723635
Simultaneous formation of charge storage and bitline to wordline isolation Nov 27, 2000 Issued
Array ( [id] => 1435905 [patent_doc_number] => 06355548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method for manufacturing a gate structure incorporated therein a high K dielectric' [patent_app_type] => B1 [patent_app_number] => 09/722465 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1327 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355548.pdf [firstpage_image] =>[orig_patent_app_number] => 09722465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722465
Method for manufacturing a gate structure incorporated therein a high K dielectric Nov 27, 2000 Issued
Array ( [id] => 1418153 [patent_doc_number] => 06514826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method of forming a gate electrode in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/721636 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514826.pdf [firstpage_image] =>[orig_patent_app_number] => 09721636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/721636
Method of forming a gate electrode in a semiconductor device Nov 26, 2000 Issued
Array ( [id] => 1578229 [patent_doc_number] => 06448164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Dark field image reversal for gate or line patterning' [patent_app_type] => B1 [patent_app_number] => 09/716216 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1974 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448164.pdf [firstpage_image] =>[orig_patent_app_number] => 09716216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716216
Dark field image reversal for gate or line patterning Nov 20, 2000 Issued
Array ( [id] => 1549671 [patent_doc_number] => 06346445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method for fabricating semiconductor devices with dual gate oxides' [patent_app_type] => B1 [patent_app_number] => 09/715826 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2178 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346445.pdf [firstpage_image] =>[orig_patent_app_number] => 09715826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715826
Method for fabricating semiconductor devices with dual gate oxides Nov 16, 2000 Issued
Array ( [id] => 1441012 [patent_doc_number] => 06495889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Semiconductor device having self-aligned contacts' [patent_app_type] => B1 [patent_app_number] => 09/713025 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 7258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495889.pdf [firstpage_image] =>[orig_patent_app_number] => 09713025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713025
Semiconductor device having self-aligned contacts Nov 15, 2000 Issued
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