Darlington Ly

Array ( [id] => 944094 [patent_doc_number] => 06967147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor' [patent_app_type] => utility [patent_app_number] => 09/714356 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2367 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967147.pdf [firstpage_image] =>[orig_patent_app_number] => 09714356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565810 [patent_doc_number] => 06376320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate' [patent_app_type] => B1 [patent_app_number] => 09/712995 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4913 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376320.pdf [firstpage_image] =>[orig_patent_app_number] => 09712995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507297 [patent_doc_number] => 06440789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits' [patent_app_type] => B1 [patent_app_number] => 09/704026 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 32 [patent_no_of_words] => 2712 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440789.pdf [firstpage_image] =>[orig_patent_app_number] => 09704026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1385518 [patent_doc_number] => 06548343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of fabricating a ferroelectric memory cell' [patent_app_type] => B1 [patent_app_number] => 09/702985 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 13108 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548343.pdf [firstpage_image] =>[orig_patent_app_number] => 09702985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1474489 [patent_doc_number] => 06387756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Manufacturing method of non-volatile semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/698245 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2286 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387756.pdf [firstpage_image] =>[orig_patent_app_number] => 09698245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459361 [patent_doc_number] => 06391715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for forming a capacitor' [patent_app_type] => B1 [patent_app_number] => 09/697515 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2932 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391715.pdf [firstpage_image] =>[orig_patent_app_number] => 09697515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1542559 [patent_doc_number] => 06372578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Manufacturing method of non-volatile semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/695085 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4248 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372578.pdf [firstpage_image] =>[orig_patent_app_number] => 09695085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424099 [patent_doc_number] => 06507058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same' [patent_app_type] => B1 [patent_app_number] => 09/690876 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1959 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507058.pdf [firstpage_image] =>[orig_patent_app_number] => 09690876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595453 [patent_doc_number] => 06492218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Use of a hard mask in the manufacture of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/680716 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2316 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492218.pdf [firstpage_image] =>[orig_patent_app_number] => 09680716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1202674 [patent_doc_number] => 06720225 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Reactive pre-clean using reducing gas during nickel silicide process' [patent_app_type] => B1 [patent_app_number] => 09/679883 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 5220 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720225.pdf [firstpage_image] =>[orig_patent_app_number] => 09679883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4321787 [patent_doc_number] => 06331464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method of fabricating a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/677166 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1208 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331464.pdf [firstpage_image] =>[orig_patent_app_number] => 677166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415817 [patent_doc_number] => 06518130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method for forming a semiconductor device having a DRAM region and a logic region on the substrate' [patent_app_type] => B1 [patent_app_number] => 09/672876 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 70 [patent_no_of_words] => 19023 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518130.pdf [firstpage_image] =>[orig_patent_app_number] => 09672876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1188857 [patent_doc_number] => 06734088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Control of two-step gate etch process' [patent_app_type] => B1 [patent_app_number] => 09/661536 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3613 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734088.pdf [firstpage_image] =>[orig_patent_app_number] => 09661536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408246 [patent_doc_number] => 06265270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method for fabricating mask ROM via medium current implanter' [patent_app_type] => 1 [patent_app_number] => 9/659359 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2783 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265270.pdf [firstpage_image] =>[orig_patent_app_number] => 659359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1559687 [patent_doc_number] => 06436761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for manufacturing semiconductor memory devices' [patent_app_type] => B1 [patent_app_number] => 09/658986 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5859 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436761.pdf [firstpage_image] =>[orig_patent_app_number] => 09658986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1578140 [patent_doc_number] => 06448141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Graded LDD implant process for sub-half-micron MOS devices' [patent_app_type] => B1 [patent_app_number] => 09/649246 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2446 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448141.pdf [firstpage_image] =>[orig_patent_app_number] => 09649246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446604 [patent_doc_number] => 06368940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method for fabricating a microelectronic structure' [patent_app_type] => B1 [patent_app_number] => 09/642325 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3291 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368940.pdf [firstpage_image] =>[orig_patent_app_number] => 09642325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424117 [patent_doc_number] => 06503788 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Semiconductor device and method of manufacture thereof' [patent_app_type] => B1 [patent_app_number] => 09/639306 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503788.pdf [firstpage_image] =>[orig_patent_app_number] => 09639306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4394752 [patent_doc_number] => 06297105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method of forming asymmetric source/drain for a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/595265 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2119 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297105.pdf [firstpage_image] =>[orig_patent_app_number] => 595265 [rel_patent_id] =>[rel_patent_doc_number] =>)