Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4451580 [patent_doc_number] => 07964905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-21 [patent_title] => 'Anti-reflective interpoly dielectric' [patent_app_type] => utility [patent_app_number] => 09/591266 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1243 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964905.pdf [firstpage_image] =>[orig_patent_app_number] => 09591266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/591266
Anti-reflective interpoly dielectric Jun 8, 2000 Issued
Array ( [id] => 4258396 [patent_doc_number] => 06204133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Self-aligned extension junction for reduced gate channel' [patent_app_type] => 1 [patent_app_number] => 9/586516 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 3452 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204133.pdf [firstpage_image] =>[orig_patent_app_number] => 586516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586516
Self-aligned extension junction for reduced gate channel Jun 1, 2000 Issued
Array ( [id] => 1123434 [patent_doc_number] => 06794279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas' [patent_app_type] => B1 [patent_app_number] => 09/577706 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4441 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794279.pdf [firstpage_image] =>[orig_patent_app_number] => 09577706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577706
Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas May 22, 2000 Issued
Array ( [id] => 1375820 [patent_doc_number] => 06559019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Breakdown drain extended NMOS' [patent_app_type] => B1 [patent_app_number] => 09/572785 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1386 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559019.pdf [firstpage_image] =>[orig_patent_app_number] => 09572785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572785
Breakdown drain extended NMOS May 16, 2000 Issued
Array ( [id] => 1477611 [patent_doc_number] => 06344381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Method for forming pillar CMOS' [patent_app_type] => B1 [patent_app_number] => 09/561670 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 3775 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344381.pdf [firstpage_image] =>[orig_patent_app_number] => 09561670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561670
Method for forming pillar CMOS Apr 30, 2000 Issued
Array ( [id] => 1458749 [patent_doc_number] => 06426257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Flash memory and manufacturing method therefor' [patent_app_type] => B1 [patent_app_number] => 09/552226 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3002 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426257.pdf [firstpage_image] =>[orig_patent_app_number] => 09552226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552226
Flash memory and manufacturing method therefor Apr 18, 2000 Issued
Array ( [id] => 1375644 [patent_doc_number] => 06559007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide' [patent_app_type] => B1 [patent_app_number] => 09/544505 [patent_app_country] => US [patent_app_date] => 2000-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3778 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559007.pdf [firstpage_image] =>[orig_patent_app_number] => 09544505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/544505
Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide Apr 5, 2000 Issued
Array ( [id] => 6896189 [patent_doc_number] => 20010026979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method of performing threshold voltage adjustment for MOS transistors' [patent_app_type] => new [patent_app_number] => 09/537175 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026979.pdf [firstpage_image] =>[orig_patent_app_number] => 09537175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537175
Method of performing threshold voltage adjustment for MOS transistors Mar 28, 2000 Issued
09/527596 Manufacturing method of a semiconductor device Mar 16, 2000 Abandoned
Array ( [id] => 4408080 [patent_doc_number] => 06265255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Ultra-shallow junction formation for deep sub-micron complementary metal-oxide-semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/531095 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2598 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265255.pdf [firstpage_image] =>[orig_patent_app_number] => 531095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531095
Ultra-shallow junction formation for deep sub-micron complementary metal-oxide-semiconductor Mar 16, 2000 Issued
09/524513 Method for forming wells in semiconductor device Mar 12, 2000 Abandoned
Array ( [id] => 1441006 [patent_doc_number] => 06335244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method for producing nonvolatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/523176 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4896 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335244.pdf [firstpage_image] =>[orig_patent_app_number] => 09523176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523176
Method for producing nonvolatile semiconductor memory device Mar 9, 2000 Issued
Array ( [id] => 1578262 [patent_doc_number] => 06448172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Manufacturing method of forming interconnection in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/512246 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 2928 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448172.pdf [firstpage_image] =>[orig_patent_app_number] => 09512246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512246
Manufacturing method of forming interconnection in semiconductor device Feb 23, 2000 Issued
Array ( [id] => 4417085 [patent_doc_number] => 06194266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method for forming a capacitor having selective hemispherical grained polysilicon' [patent_app_type] => 1 [patent_app_number] => 9/511656 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1577 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194266.pdf [firstpage_image] =>[orig_patent_app_number] => 511656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511656
Method for forming a capacitor having selective hemispherical grained polysilicon Feb 21, 2000 Issued
Array ( [id] => 4377719 [patent_doc_number] => 06303447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method for forming an extended metal gate using a damascene process' [patent_app_type] => 1 [patent_app_number] => 9/502036 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 4025 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303447.pdf [firstpage_image] =>[orig_patent_app_number] => 502036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/502036
Method for forming an extended metal gate using a damascene process Feb 10, 2000 Issued
Array ( [id] => 1419264 [patent_doc_number] => 06506662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method for forming an SOI substrate by use of a plasma ion irradiation' [patent_app_type] => B2 [patent_app_number] => 09/501532 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5484 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506662.pdf [firstpage_image] =>[orig_patent_app_number] => 09501532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501532
Method for forming an SOI substrate by use of a plasma ion irradiation Feb 8, 2000 Issued
Array ( [id] => 1542576 [patent_doc_number] => 06372583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Process for making semiconductor device with epitaxially grown source and drain' [patent_app_type] => B1 [patent_app_number] => 09/500556 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2947 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372583.pdf [firstpage_image] =>[orig_patent_app_number] => 09500556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500556
Process for making semiconductor device with epitaxially grown source and drain Feb 8, 2000 Issued
Array ( [id] => 1565736 [patent_doc_number] => 06376303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of manufacturing a capacitor having oxide layers with different impurities and method of fabricating a semiconductor device comprising the same' [patent_app_type] => B1 [patent_app_number] => 09/499295 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 7554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376303.pdf [firstpage_image] =>[orig_patent_app_number] => 09499295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499295
Method of manufacturing a capacitor having oxide layers with different impurities and method of fabricating a semiconductor device comprising the same Feb 6, 2000 Issued
Array ( [id] => 4327174 [patent_doc_number] => 06319807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method for forming a semiconductor device by using reverse-offset spacer process' [patent_app_type] => 1 [patent_app_number] => 9/498861 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1839 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319807.pdf [firstpage_image] =>[orig_patent_app_number] => 498861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/498861
Method for forming a semiconductor device by using reverse-offset spacer process Feb 6, 2000 Issued
Array ( [id] => 4286047 [patent_doc_number] => 06211024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for forming a semiconductor device by using multiple ion implantation sequence to reduce crystal defects and to allow the reduction of the temperature used for a subsequent rapid thermal anneal procedure' [patent_app_type] => 1 [patent_app_number] => 9/495345 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1901 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211024.pdf [firstpage_image] =>[orig_patent_app_number] => 495345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495345
Method for forming a semiconductor device by using multiple ion implantation sequence to reduce crystal defects and to allow the reduction of the temperature used for a subsequent rapid thermal anneal procedure Jan 31, 2000 Issued
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