Darlington Ly

Array ( [id] => 4182425 [patent_doc_number] => 06150235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method of forming shallow trench isolation structures' [patent_app_type] => 1 [patent_app_number] => 9/490275 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3973 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150235.pdf [firstpage_image] =>[orig_patent_app_number] => 490275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4086818 [patent_doc_number] => 06133088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of forming crown-shaped capacitor' [patent_app_type] => 1 [patent_app_number] => 9/488955 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2962 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133088.pdf [firstpage_image] =>[orig_patent_app_number] => 488955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462474 [patent_doc_number] => 06350646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method for reducing thermal budget in node contact application' [patent_app_type] => B1 [patent_app_number] => 09/484786 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1637 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350646.pdf [firstpage_image] =>[orig_patent_app_number] => 09484786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1542525 [patent_doc_number] => 06372569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance' [patent_app_type] => B1 [patent_app_number] => 09/483035 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2152 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372569.pdf [firstpage_image] =>[orig_patent_app_number] => 09483035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417014 [patent_doc_number] => 06194258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method of forming an image sensor cell and a CMOS logic circuit device' [patent_app_type] => 1 [patent_app_number] => 9/483935 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2871 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194258.pdf [firstpage_image] =>[orig_patent_app_number] => 483935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4344525 [patent_doc_number] => 06284635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for forming titanium polycide gate' [patent_app_type] => 1 [patent_app_number] => 9/471596 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1499 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284635.pdf [firstpage_image] =>[orig_patent_app_number] => 471596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1532488 [patent_doc_number] => 06410394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for forming self-aligned channel implants using a gate poly reverse mask' [patent_app_type] => B1 [patent_app_number] => 09/465305 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3099 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410394.pdf [firstpage_image] =>[orig_patent_app_number] => 09465305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4182534 [patent_doc_number] => 06150244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for fabricating MOS transistor having raised source and drain' [patent_app_type] => 1 [patent_app_number] => 9/467086 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150244.pdf [firstpage_image] =>[orig_patent_app_number] => 467086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381178 [patent_doc_number] => 06261907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of forming a flash EEPROM device by employing polysilicon sidewall spacer as an erase gate' [patent_app_type] => 1 [patent_app_number] => 9/453395 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4881 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261907.pdf [firstpage_image] =>[orig_patent_app_number] => 453395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326772 [patent_doc_number] => 06319783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Process to fabricate a novel source-drain extension' [patent_app_type] => 1 [patent_app_number] => 9/443425 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3719 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319783.pdf [firstpage_image] =>[orig_patent_app_number] => 443425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303845 [patent_doc_number] => 06326272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for forming self-aligned elevated transistor' [patent_app_type] => 1 [patent_app_number] => 9/442496 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326272.pdf [firstpage_image] =>[orig_patent_app_number] => 442496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237394 [patent_doc_number] => 06090691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for forming a raised source and drain without using selective epitaxial growth' [patent_app_type] => 1 [patent_app_number] => 9/439366 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4015 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090691.pdf [firstpage_image] =>[orig_patent_app_number] => 439366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185543 [patent_doc_number] => 06093600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method of fabricating a dynamic random-access memory device' [patent_app_type] => 1 [patent_app_number] => 9/430706 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3162 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093600.pdf [firstpage_image] =>[orig_patent_app_number] => 430706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291901 [patent_doc_number] => 06180454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method for forming flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/430765 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180454.pdf [firstpage_image] =>[orig_patent_app_number] => 430765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1043664 [patent_doc_number] => 06867097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method of making a memory cell with polished insulator layer' [patent_app_type] => utility [patent_app_number] => 09/430366 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1764 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867097.pdf [firstpage_image] =>[orig_patent_app_number] => 09430366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318692 [patent_doc_number] => 06248635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Process for fabricating a bit-line in a monos device using a dual layer hard mask' [patent_app_type] => 1 [patent_app_number] => 9/426205 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2335 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248635.pdf [firstpage_image] =>[orig_patent_app_number] => 426205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139139 [patent_doc_number] => 06060353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of forming a ring shaped storage node structure for a DRAM capacitor structure' [patent_app_type] => 1 [patent_app_number] => 9/422176 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060353.pdf [firstpage_image] =>[orig_patent_app_number] => 422176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405403 [patent_doc_number] => 06232181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method of forming a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/422625 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2107 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232181.pdf [firstpage_image] =>[orig_patent_app_number] => 422625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4245779 [patent_doc_number] => 06136650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of forming three-dimensional flash memory structure' [patent_app_type] => 1 [patent_app_number] => 9/422626 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3088 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136650.pdf [firstpage_image] =>[orig_patent_app_number] => 422626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4099888 [patent_doc_number] => 06066532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method of fabricating embedded gate electrodes' [patent_app_type] => 1 [patent_app_number] => 9/419434 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2413 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066532.pdf [firstpage_image] =>[orig_patent_app_number] => 419434 [rel_patent_id] =>[rel_patent_doc_number] =>)