Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4286721 [patent_doc_number] => 06268253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Forming a removable spacer of uniform width on sidewalls of a gate of a field effect transistor during a differential rapid thermal anneal process' [patent_app_type] => 1 [patent_app_number] => 9/418407 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4227 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268253.pdf [firstpage_image] =>[orig_patent_app_number] => 418407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418407
Forming a removable spacer of uniform width on sidewalls of a gate of a field effect transistor during a differential rapid thermal anneal process Oct 13, 1999 Issued
Array ( [id] => 4215428 [patent_doc_number] => 06087235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for effective fabrication of a field effect transistor with elevated drain and source contact structures' [patent_app_type] => 1 [patent_app_number] => 9/418276 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4124 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087235.pdf [firstpage_image] =>[orig_patent_app_number] => 418276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418276
Method for effective fabrication of a field effect transistor with elevated drain and source contact structures Oct 13, 1999 Issued
Array ( [id] => 4292575 [patent_doc_number] => 06180501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process' [patent_app_type] => 1 [patent_app_number] => 9/418036 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4860 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180501.pdf [firstpage_image] =>[orig_patent_app_number] => 418036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418036
Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process Oct 13, 1999 Issued
Array ( [id] => 4318441 [patent_doc_number] => 06248618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method of fabrication of dual gate oxides for CMOS devices' [patent_app_type] => 1 [patent_app_number] => 9/415246 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1927 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248618.pdf [firstpage_image] =>[orig_patent_app_number] => 415246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415246
Method of fabrication of dual gate oxides for CMOS devices Oct 11, 1999 Issued
Array ( [id] => 4259007 [patent_doc_number] => 06258677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of fabricating wedge isolation transistors' [patent_app_type] => 1 [patent_app_number] => 9/409875 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2066 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258677.pdf [firstpage_image] =>[orig_patent_app_number] => 409875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409875
Method of fabricating wedge isolation transistors Sep 30, 1999 Issued
Array ( [id] => 4357973 [patent_doc_number] => 06255152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of fabricating CMOS using Si-B layer to form source/drain extension junction' [patent_app_type] => 1 [patent_app_number] => 9/410690 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3539 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255152.pdf [firstpage_image] =>[orig_patent_app_number] => 410690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410690
Method of fabricating CMOS using Si-B layer to form source/drain extension junction Sep 30, 1999 Issued
Array ( [id] => 4408001 [patent_doc_number] => 06300172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method of field isolation in silicon-on-insulator technology' [patent_app_type] => 1 [patent_app_number] => 9/409887 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1708 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300172.pdf [firstpage_image] =>[orig_patent_app_number] => 409887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409887
Method of field isolation in silicon-on-insulator technology Sep 30, 1999 Issued
Array ( [id] => 4419384 [patent_doc_number] => 06177307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Process of planarizing crown capacitor for integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/392158 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177307.pdf [firstpage_image] =>[orig_patent_app_number] => 392158 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392158
Process of planarizing crown capacitor for integrated circuit Sep 7, 1999 Issued
Array ( [id] => 4214496 [patent_doc_number] => 06110787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method for fabricating a MOS device' [patent_app_type] => 1 [patent_app_number] => 9/391886 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1905 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110787.pdf [firstpage_image] =>[orig_patent_app_number] => 391886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391886
Method for fabricating a MOS device Sep 6, 1999 Issued
Array ( [id] => 4218965 [patent_doc_number] => 06040223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/373636 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040223.pdf [firstpage_image] =>[orig_patent_app_number] => 373636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373636
Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits Aug 12, 1999 Issued
Array ( [id] => 4099818 [patent_doc_number] => 06066527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Buried strap poly etch back (BSPE) process' [patent_app_type] => 1 [patent_app_number] => 9/361055 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2929 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066527.pdf [firstpage_image] =>[orig_patent_app_number] => 361055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361055
Buried strap poly etch back (BSPE) process Jul 25, 1999 Issued
Array ( [id] => 4347754 [patent_doc_number] => 06214670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance' [patent_app_type] => 1 [patent_app_number] => 9/358986 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2530 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214670.pdf [firstpage_image] =>[orig_patent_app_number] => 358986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358986
Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance Jul 21, 1999 Issued
Array ( [id] => 4419498 [patent_doc_number] => 06177319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method of manufacturing salicide layer' [patent_app_type] => 1 [patent_app_number] => 9/345435 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177319.pdf [firstpage_image] =>[orig_patent_app_number] => 345435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345435
Method of manufacturing salicide layer Jun 30, 1999 Issued
Array ( [id] => 1549696 [patent_doc_number] => 06346450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Process for manufacturing MIS transistor with self-aligned metal grid' [patent_app_type] => B1 [patent_app_number] => 09/319915 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 6561 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346450.pdf [firstpage_image] =>[orig_patent_app_number] => 09319915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/319915
Process for manufacturing MIS transistor with self-aligned metal grid Jun 27, 1999 Issued
Array ( [id] => 1462494 [patent_doc_number] => 06350651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method for making flash memory with UV opaque passivation layer' [patent_app_type] => B1 [patent_app_number] => 09/330257 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1831 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350651.pdf [firstpage_image] =>[orig_patent_app_number] => 09330257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330257
Method for making flash memory with UV opaque passivation layer Jun 9, 1999 Issued
Array ( [id] => 6961311 [patent_doc_number] => 20010012659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CAPACITOR' [patent_app_type] => new [patent_app_number] => 09/321605 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012659.pdf [firstpage_image] =>[orig_patent_app_number] => 09321605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321605
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CAPACITOR May 27, 1999 Abandoned
Array ( [id] => 4394912 [patent_doc_number] => 06297115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Cmos processs with low thermal budget' [patent_app_type] => 1 [patent_app_number] => 9/303696 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3090 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297115.pdf [firstpage_image] =>[orig_patent_app_number] => 303696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303696
Cmos processs with low thermal budget May 2, 1999 Issued
Array ( [id] => 3937146 [patent_doc_number] => 05981325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method for manufacturing CMOS' [patent_app_type] => 1 [patent_app_number] => 9/299255 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2382 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981325.pdf [firstpage_image] =>[orig_patent_app_number] => 299255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299255
Method for manufacturing CMOS Apr 25, 1999 Issued
Array ( [id] => 4347937 [patent_doc_number] => 06214683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Process for fabricating a semiconductor device component using lateral metal oxidation' [patent_app_type] => 1 [patent_app_number] => 9/290555 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3190 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214683.pdf [firstpage_image] =>[orig_patent_app_number] => 290555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290555
Process for fabricating a semiconductor device component using lateral metal oxidation Apr 11, 1999 Issued
Array ( [id] => 4353757 [patent_doc_number] => 06218246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Fabrication method of triple polysilicon flash eeprom arrays' [patent_app_type] => 1 [patent_app_number] => 9/285886 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 2541 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218246.pdf [firstpage_image] =>[orig_patent_app_number] => 285886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285886
Fabrication method of triple polysilicon flash eeprom arrays Apr 6, 1999 Issued
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