Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4353446 [patent_doc_number] => 06218224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Nitride disposable spacer to reduce mask count in CMOS transistor formation' [patent_app_type] => 1 [patent_app_number] => 9/276725 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3821 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218224.pdf [firstpage_image] =>[orig_patent_app_number] => 276725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276725
Nitride disposable spacer to reduce mask count in CMOS transistor formation Mar 25, 1999 Issued
Array ( [id] => 4354581 [patent_doc_number] => 06200861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method of fabricating high density multiple states mask ROM cells' [patent_app_type] => 1 [patent_app_number] => 9/276646 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2599 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200861.pdf [firstpage_image] =>[orig_patent_app_number] => 276646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276646
Method of fabricating high density multiple states mask ROM cells Mar 25, 1999 Issued
Array ( [id] => 6882696 [patent_doc_number] => 20010049168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'MANUFACTURE OF A SEMICONDUCTOR DEVICE WITH RETROGRADED WELLS' [patent_app_type] => new [patent_app_number] => 09/276795 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8014 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049168.pdf [firstpage_image] =>[orig_patent_app_number] => 09276795 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276795
Manufacture of a semiconductor device with retrograded wells Mar 25, 1999 Issued
Array ( [id] => 3935110 [patent_doc_number] => 05972764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method for manufacturing MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/270026 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2746 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972764.pdf [firstpage_image] =>[orig_patent_app_number] => 270026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270026
Method for manufacturing MOS transistor Mar 15, 1999 Issued
Array ( [id] => 4405671 [patent_doc_number] => 06171899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method for fabricating a capacitor' [patent_app_type] => 1 [patent_app_number] => 9/267535 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2351 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171899.pdf [firstpage_image] =>[orig_patent_app_number] => 267535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267535
Method for fabricating a capacitor Mar 11, 1999 Issued
Array ( [id] => 4083867 [patent_doc_number] => 06162684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/266714 [patent_app_country] => US [patent_app_date] => 1999-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 5290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162684.pdf [firstpage_image] =>[orig_patent_app_number] => 266714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266714
Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices Mar 10, 1999 Issued
Array ( [id] => 4145457 [patent_doc_number] => 06063657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method of forming a buried strap in a DRAM' [patent_app_type] => 1 [patent_app_number] => 9/255535 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063657.pdf [firstpage_image] =>[orig_patent_app_number] => 255535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255535
Method of forming a buried strap in a DRAM Feb 21, 1999 Issued
Array ( [id] => 4404795 [patent_doc_number] => 06271095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Locally confined deep pocket process for ULSI mosfets' [patent_app_type] => 1 [patent_app_number] => 9/255546 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3454 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271095.pdf [firstpage_image] =>[orig_patent_app_number] => 255546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255546
Locally confined deep pocket process for ULSI mosfets Feb 21, 1999 Issued
Array ( [id] => 4294103 [patent_doc_number] => 06184097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Process for forming ultra-shallow source/drain extensions' [patent_app_type] => 1 [patent_app_number] => 9/255604 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184097.pdf [firstpage_image] =>[orig_patent_app_number] => 255604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255604
Process for forming ultra-shallow source/drain extensions Feb 21, 1999 Issued
Array ( [id] => 1550297 [patent_doc_number] => 06399439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/252885 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5702 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399439.pdf [firstpage_image] =>[orig_patent_app_number] => 09252885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252885
Method for manufacturing semiconductor device Feb 17, 1999 Issued
Array ( [id] => 4294069 [patent_doc_number] => 06184095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for fabricating mask ROM via medium current implanter' [patent_app_type] => 1 [patent_app_number] => 9/247746 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2783 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184095.pdf [firstpage_image] =>[orig_patent_app_number] => 247746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247746
Method for fabricating mask ROM via medium current implanter Feb 8, 1999 Issued
Array ( [id] => 1549660 [patent_doc_number] => 06346442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array' [patent_app_type] => B1 [patent_app_number] => 09/244316 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6900 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346442.pdf [firstpage_image] =>[orig_patent_app_number] => 09244316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244316
Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array Feb 3, 1999 Issued
Array ( [id] => 4238123 [patent_doc_number] => 06080630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for forming a MOS device with self-compensating V.sub.T -implants' [patent_app_type] => 1 [patent_app_number] => 9/243014 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 5206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080630.pdf [firstpage_image] =>[orig_patent_app_number] => 243014 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243014
Method for forming a MOS device with self-compensating V.sub.T -implants Feb 2, 1999 Issued
Array ( [id] => 4358860 [patent_doc_number] => 06168998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Dual gate MOSFET fabrication method' [patent_app_type] => 1 [patent_app_number] => 9/243534 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1387 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/168/06168998.pdf [firstpage_image] =>[orig_patent_app_number] => 243534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243534
Dual gate MOSFET fabrication method Feb 2, 1999 Issued
Array ( [id] => 4141717 [patent_doc_number] => 06030872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method of fabricating mixed-mode device' [patent_app_type] => 1 [patent_app_number] => 9/241545 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2262 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030872.pdf [firstpage_image] =>[orig_patent_app_number] => 241545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241545
Method of fabricating mixed-mode device Jan 31, 1999 Issued
Array ( [id] => 4293983 [patent_doc_number] => 06184089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method of fabricating one-time programmable read only memory' [patent_app_type] => 1 [patent_app_number] => 9/239034 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2217 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184089.pdf [firstpage_image] =>[orig_patent_app_number] => 239034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239034
Method of fabricating one-time programmable read only memory Jan 26, 1999 Issued
Array ( [id] => 4233885 [patent_doc_number] => 06074919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of forming an ultrathin gate dielectric' [patent_app_type] => 1 [patent_app_number] => 9/234561 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074919.pdf [firstpage_image] =>[orig_patent_app_number] => 234561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234561
Method of forming an ultrathin gate dielectric Jan 19, 1999 Issued
Array ( [id] => 4302702 [patent_doc_number] => 06187645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation' [patent_app_type] => 1 [patent_app_number] => 9/233354 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187645.pdf [firstpage_image] =>[orig_patent_app_number] => 233354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233354
Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation Jan 18, 1999 Issued
Array ( [id] => 1419044 [patent_doc_number] => 06506644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method of fabricating semiconductor having a reduced leakage current flow between the accumulation electrode and the gate electrode' [patent_app_type] => B2 [patent_app_number] => 09/228566 [patent_app_country] => US [patent_app_date] => 1999-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 39 [patent_no_of_words] => 8368 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506644.pdf [firstpage_image] =>[orig_patent_app_number] => 09228566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/228566
Method of fabricating semiconductor having a reduced leakage current flow between the accumulation electrode and the gate electrode Jan 11, 1999 Issued
Array ( [id] => 1559647 [patent_doc_number] => 06436746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Transistor having an improved gate structure and method of construction' [patent_app_type] => B1 [patent_app_number] => 09/225405 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 4054 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436746.pdf [firstpage_image] =>[orig_patent_app_number] => 09225405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225405
Transistor having an improved gate structure and method of construction Jan 4, 1999 Issued
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