
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4353446
[patent_doc_number] => 06218224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Nitride disposable spacer to reduce mask count in CMOS transistor formation'
[patent_app_type] => 1
[patent_app_number] => 9/276725
[patent_app_country] => US
[patent_app_date] => 1999-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3821
[patent_no_of_claims] => 19
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/218/06218224.pdf
[firstpage_image] =>[orig_patent_app_number] => 276725
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/276725 | Nitride disposable spacer to reduce mask count in CMOS transistor formation | Mar 25, 1999 | Issued |
Array
(
[id] => 4354581
[patent_doc_number] => 06200861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'Method of fabricating high density multiple states mask ROM cells'
[patent_app_type] => 1
[patent_app_number] => 9/276646
[patent_app_country] => US
[patent_app_date] => 1999-03-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/200/06200861.pdf
[firstpage_image] =>[orig_patent_app_number] => 276646
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/276646 | Method of fabricating high density multiple states mask ROM cells | Mar 25, 1999 | Issued |
Array
(
[id] => 6882696
[patent_doc_number] => 20010049168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-06
[patent_title] => 'MANUFACTURE OF A SEMICONDUCTOR DEVICE WITH RETROGRADED WELLS'
[patent_app_type] => new
[patent_app_number] => 09/276795
[patent_app_country] => US
[patent_app_date] => 1999-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0049/20010049168.pdf
[firstpage_image] =>[orig_patent_app_number] => 09276795
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/276795 | Manufacture of a semiconductor device with retrograded wells | Mar 25, 1999 | Issued |
Array
(
[id] => 3935110
[patent_doc_number] => 05972764
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Method for manufacturing MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 9/270026
[patent_app_country] => US
[patent_app_date] => 1999-03-16
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 270026
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/270026 | Method for manufacturing MOS transistor | Mar 15, 1999 | Issued |
Array
(
[id] => 4405671
[patent_doc_number] => 06171899
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[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Method for fabricating a capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/267535
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/171/06171899.pdf
[firstpage_image] =>[orig_patent_app_number] => 267535
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/267535 | Method for fabricating a capacitor | Mar 11, 1999 | Issued |
Array
(
[id] => 4083867
[patent_doc_number] => 06162684
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices'
[patent_app_type] => 1
[patent_app_number] => 9/266714
[patent_app_country] => US
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[pdf_file] => patents/06/162/06162684.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/266714 | Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices | Mar 10, 1999 | Issued |
Array
(
[id] => 4145457
[patent_doc_number] => 06063657
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Method of forming a buried strap in a DRAM'
[patent_app_type] => 1
[patent_app_number] => 9/255535
[patent_app_country] => US
[patent_app_date] => 1999-02-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/063/06063657.pdf
[firstpage_image] =>[orig_patent_app_number] => 255535
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/255535 | Method of forming a buried strap in a DRAM | Feb 21, 1999 | Issued |
Array
(
[id] => 4404795
[patent_doc_number] => 06271095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Locally confined deep pocket process for ULSI mosfets'
[patent_app_type] => 1
[patent_app_number] => 9/255546
[patent_app_country] => US
[patent_app_date] => 1999-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/271/06271095.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/255546 | Locally confined deep pocket process for ULSI mosfets | Feb 21, 1999 | Issued |
Array
(
[id] => 4294103
[patent_doc_number] => 06184097
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Process for forming ultra-shallow source/drain extensions'
[patent_app_type] => 1
[patent_app_number] => 9/255604
[patent_app_country] => US
[patent_app_date] => 1999-02-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 255604
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/255604 | Process for forming ultra-shallow source/drain extensions | Feb 21, 1999 | Issued |
Array
(
[id] => 1550297
[patent_doc_number] => 06399439
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/252885
[patent_app_country] => US
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Array
(
[id] => 4294069
[patent_doc_number] => 06184095
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[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Method for fabricating mask ROM via medium current implanter'
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Array
(
[id] => 1549660
[patent_doc_number] => 06346442
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[patent_title] => 'Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array'
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Array
(
[id] => 4238123
[patent_doc_number] => 06080630
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[patent_title] => 'Method for forming a MOS device with self-compensating V.sub.T -implants'
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[patent_app_number] => 9/243014
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Array
(
[id] => 4358860
[patent_doc_number] => 06168998
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[patent_title] => 'Dual gate MOSFET fabrication method'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/241545 | Method of fabricating mixed-mode device | Jan 31, 1999 | Issued |
Array
(
[id] => 4293983
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Array
(
[id] => 4233885
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225405 | Transistor having an improved gate structure and method of construction | Jan 4, 1999 | Issued |