Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
09/221154 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH ELEVATED SOURCE/DRAIN REGIONS Dec 27, 1998 Abandoned
Array ( [id] => 4303105 [patent_doc_number] => 06187674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Manufacturing method capable of preventing corrosion and contamination of MOS gate' [patent_app_type] => 1 [patent_app_number] => 9/208605 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187674.pdf [firstpage_image] =>[orig_patent_app_number] => 208605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208605
Manufacturing method capable of preventing corrosion and contamination of MOS gate Dec 7, 1998 Issued
Array ( [id] => 3943413 [patent_doc_number] => 05976923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method for fabricating a high-voltage semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/209366 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1951 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976923.pdf [firstpage_image] =>[orig_patent_app_number] => 209366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209366
Method for fabricating a high-voltage semiconductor device Dec 7, 1998 Issued
Array ( [id] => 4004183 [patent_doc_number] => 05960282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method for fabricating a dynamic random access memory with a vertical pass transistor' [patent_app_type] => 1 [patent_app_number] => 9/206065 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960282.pdf [firstpage_image] =>[orig_patent_app_number] => 206065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206065
Method for fabricating a dynamic random access memory with a vertical pass transistor Dec 3, 1998 Issued
Array ( [id] => 4394898 [patent_doc_number] => 06297114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Semiconductor device and process and apparatus of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/205754 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 30 [patent_no_of_words] => 17010 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297114.pdf [firstpage_image] =>[orig_patent_app_number] => 205754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205754
Semiconductor device and process and apparatus of fabricating the same Dec 3, 1998 Issued
Array ( [id] => 4302605 [patent_doc_number] => 06187638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method for manufacturing memory cell with increased threshold voltage accuracy' [patent_app_type] => 1 [patent_app_number] => 9/205704 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1669 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187638.pdf [firstpage_image] =>[orig_patent_app_number] => 205704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205704
Method for manufacturing memory cell with increased threshold voltage accuracy Dec 3, 1998 Issued
Array ( [id] => 4310166 [patent_doc_number] => 06316311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method of forming borderless contact' [patent_app_type] => 1 [patent_app_number] => 9/203036 [patent_app_country] => US [patent_app_date] => 1998-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1605 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316311.pdf [firstpage_image] =>[orig_patent_app_number] => 203036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203036
Method of forming borderless contact Nov 30, 1998 Issued
Array ( [id] => 4381219 [patent_doc_number] => 06261910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/201905 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4864 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261910.pdf [firstpage_image] =>[orig_patent_app_number] => 201905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/201905
Semiconductor device and method of manufacturing the same Nov 29, 1998 Issued
Array ( [id] => 3943399 [patent_doc_number] => 05976922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method for fabricating a high bias device compatible with a low bias device' [patent_app_type] => 1 [patent_app_number] => 9/200895 [patent_app_country] => US [patent_app_date] => 1998-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2524 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976922.pdf [firstpage_image] =>[orig_patent_app_number] => 200895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200895
Method for fabricating a high bias device compatible with a low bias device Nov 26, 1998 Issued
Array ( [id] => 4405274 [patent_doc_number] => 06232169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for producing a capacitor' [patent_app_type] => 1 [patent_app_number] => 9/200095 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3583 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232169.pdf [firstpage_image] =>[orig_patent_app_number] => 200095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200095
Method for producing a capacitor Nov 24, 1998 Issued
Array ( [id] => 6961343 [patent_doc_number] => 20010012670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING SAME' [patent_app_type] => new [patent_app_number] => 09/196415 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3037 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012670.pdf [firstpage_image] =>[orig_patent_app_number] => 09196415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196415
SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING SAME Nov 18, 1998 Abandoned
Array ( [id] => 4185675 [patent_doc_number] => 06093609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method for forming semiconductor device with common gate, source and well' [patent_app_type] => 1 [patent_app_number] => 9/193975 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2293 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093609.pdf [firstpage_image] =>[orig_patent_app_number] => 193975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193975
Method for forming semiconductor device with common gate, source and well Nov 17, 1998 Issued
Array ( [id] => 4188388 [patent_doc_number] => 06153483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for manufacturing MOS device' [patent_app_type] => 1 [patent_app_number] => 9/193005 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1939 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153483.pdf [firstpage_image] =>[orig_patent_app_number] => 193005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193005
Method for manufacturing MOS device Nov 15, 1998 Issued
Array ( [id] => 4353932 [patent_doc_number] => 06218258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for fabricating semiconductor device including capacitor with improved bottom electrode' [patent_app_type] => 1 [patent_app_number] => 9/191374 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 3047 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218258.pdf [firstpage_image] =>[orig_patent_app_number] => 191374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191374
Method for fabricating semiconductor device including capacitor with improved bottom electrode Nov 12, 1998 Issued
Array ( [id] => 4302344 [patent_doc_number] => 06187620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions' [patent_app_type] => 1 [patent_app_number] => 9/189266 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187620.pdf [firstpage_image] =>[orig_patent_app_number] => 189266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189266
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions Nov 9, 1998 Issued
Array ( [id] => 4083779 [patent_doc_number] => 06162678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Simple small feature size bit line formation in DRAM with RTO oxidation' [patent_app_type] => 1 [patent_app_number] => 9/188916 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1441 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162678.pdf [firstpage_image] =>[orig_patent_app_number] => 188916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188916
Simple small feature size bit line formation in DRAM with RTO oxidation Nov 8, 1998 Issued
Array ( [id] => 4404744 [patent_doc_number] => 06271091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of fabricating flash memory cell' [patent_app_type] => 1 [patent_app_number] => 9/188236 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3956 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271091.pdf [firstpage_image] =>[orig_patent_app_number] => 188236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188236
Method of fabricating flash memory cell Nov 8, 1998 Issued
Array ( [id] => 3993836 [patent_doc_number] => 05985726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/187635 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2487 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985726.pdf [firstpage_image] =>[orig_patent_app_number] => 187635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187635
Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET Nov 5, 1998 Issued
Array ( [id] => 4101629 [patent_doc_number] => 06100141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for forming electrostatic discharge (ESD) protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/186305 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2545 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100141.pdf [firstpage_image] =>[orig_patent_app_number] => 186305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186305
Method for forming electrostatic discharge (ESD) protection circuit Nov 3, 1998 Issued
Array ( [id] => 4070484 [patent_doc_number] => 05970345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method of forming an integrated circuit having both low voltage and high voltage MOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/177424 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1684 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970345.pdf [firstpage_image] =>[orig_patent_app_number] => 177424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177424
Method of forming an integrated circuit having both low voltage and high voltage MOS transistors Oct 21, 1998 Issued
Menu