Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3953031 [patent_doc_number] => 05940714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method of fabricating a capacitor electrode structure in integrated circuit through self-aligned process' [patent_app_type] => 1 [patent_app_number] => 9/174805 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2246 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940714.pdf [firstpage_image] =>[orig_patent_app_number] => 174805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174805
Method of fabricating a capacitor electrode structure in integrated circuit through self-aligned process Oct 18, 1998 Issued
Array ( [id] => 4182208 [patent_doc_number] => 06150218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for simutaneously forming bit-line contacts and node contacts' [patent_app_type] => 1 [patent_app_number] => 9/175006 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1161 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150218.pdf [firstpage_image] =>[orig_patent_app_number] => 175006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175006
Method for simutaneously forming bit-line contacts and node contacts Oct 18, 1998 Issued
Array ( [id] => 4293836 [patent_doc_number] => 06184078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for fabricating a capacitor for a dynamic random access memory cell' [patent_app_type] => 1 [patent_app_number] => 9/170086 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2460 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184078.pdf [firstpage_image] =>[orig_patent_app_number] => 170086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170086
Method for fabricating a capacitor for a dynamic random access memory cell Oct 12, 1998 Issued
Array ( [id] => 1110953 [patent_doc_number] => 06806154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Method for forming a salicided MOSFET structure with tunable oxynitride spacer' [patent_app_type] => B1 [patent_app_number] => 09/169303 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3418 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806154.pdf [firstpage_image] =>[orig_patent_app_number] => 09169303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169303
Method for forming a salicided MOSFET structure with tunable oxynitride spacer Oct 7, 1998 Issued
09/163155 HIGH TEMPERATURE DEPOSITION OF OXIDE LAYER THAT PROTECTS AGAINST IMPLANTATION DAMAGE Sep 28, 1998 Abandoned
Array ( [id] => 4366151 [patent_doc_number] => 06274443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Simplified graded LDD transistor using controlled polysilicon gate profile' [patent_app_type] => 1 [patent_app_number] => 9/162116 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 56 [patent_no_of_words] => 12218 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274443.pdf [firstpage_image] =>[orig_patent_app_number] => 162116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162116
Simplified graded LDD transistor using controlled polysilicon gate profile Sep 27, 1998 Issued
Array ( [id] => 4368779 [patent_doc_number] => 06287922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for fabricating graded LDD transistor using controlled polysilicon gate profile' [patent_app_type] => 1 [patent_app_number] => 9/162426 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 56 [patent_no_of_words] => 12306 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287922.pdf [firstpage_image] =>[orig_patent_app_number] => 162426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162426
Method for fabricating graded LDD transistor using controlled polysilicon gate profile Sep 27, 1998 Issued
Array ( [id] => 1564908 [patent_doc_number] => 06339000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures' [patent_app_type] => B1 [patent_app_number] => 09/160834 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2780 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339000.pdf [firstpage_image] =>[orig_patent_app_number] => 09160834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160834
Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures Sep 24, 1998 Issued
Array ( [id] => 4050489 [patent_doc_number] => 05943575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method of forming semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/160194 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3411 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943575.pdf [firstpage_image] =>[orig_patent_app_number] => 160194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160194
Method of forming semiconductor device Sep 24, 1998 Issued
Array ( [id] => 4152069 [patent_doc_number] => 06124171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of forming gate oxide having dual thickness by oxidation process' [patent_app_type] => 1 [patent_app_number] => 9/160556 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 1835 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124171.pdf [firstpage_image] =>[orig_patent_app_number] => 160556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160556
Method of forming gate oxide having dual thickness by oxidation process Sep 23, 1998 Issued
Array ( [id] => 4249967 [patent_doc_number] => 06207519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of making semiconductor device having double spacer' [patent_app_type] => 1 [patent_app_number] => 9/158875 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2326 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207519.pdf [firstpage_image] =>[orig_patent_app_number] => 158875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158875
Method of making semiconductor device having double spacer Sep 22, 1998 Issued
Array ( [id] => 4141654 [patent_doc_number] => 06030869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method for fabricating nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/158985 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 46 [patent_no_of_words] => 10887 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030869.pdf [firstpage_image] =>[orig_patent_app_number] => 158985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158985
Method for fabricating nonvolatile semiconductor memory device Sep 22, 1998 Issued
Array ( [id] => 4016492 [patent_doc_number] => 05923986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method of forming a wide upper top spacer to prevent salicide bridge' [patent_app_type] => 1 [patent_app_number] => 9/156055 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2766 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923986.pdf [firstpage_image] =>[orig_patent_app_number] => 156055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156055
Method of forming a wide upper top spacer to prevent salicide bridge Sep 16, 1998 Issued
Array ( [id] => 3911062 [patent_doc_number] => 06001713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/154074 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4491 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001713.pdf [firstpage_image] =>[orig_patent_app_number] => 154074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154074
Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device Sep 15, 1998 Issued
Array ( [id] => 3999493 [patent_doc_number] => 05950087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method to make self-aligned source etching available in split-gate flash' [patent_app_type] => 1 [patent_app_number] => 9/151154 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3908 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950087.pdf [firstpage_image] =>[orig_patent_app_number] => 151154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151154
Method to make self-aligned source etching available in split-gate flash Sep 9, 1998 Issued
Array ( [id] => 4293704 [patent_doc_number] => 06197648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Manufacturing method of MOSFET having salicide structure' [patent_app_type] => 1 [patent_app_number] => 9/150096 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3012 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197648.pdf [firstpage_image] =>[orig_patent_app_number] => 150096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150096
Manufacturing method of MOSFET having salicide structure Sep 8, 1998 Issued
Array ( [id] => 4050502 [patent_doc_number] => 05943576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Angled implant to build MOS transistors in contact holes' [patent_app_type] => 1 [patent_app_number] => 9/145135 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 3213 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943576.pdf [firstpage_image] =>[orig_patent_app_number] => 145135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145135
Angled implant to build MOS transistors in contact holes Aug 31, 1998 Issued
Array ( [id] => 4289416 [patent_doc_number] => 06235570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/144624 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3631 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235570.pdf [firstpage_image] =>[orig_patent_app_number] => 144624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144624
Method for fabricating a semiconductor device Aug 30, 1998 Issued
Array ( [id] => 6898578 [patent_doc_number] => 20010046743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'METHOD FOR FORMING DUAL-POLYSILICON STRUCTURES USING A BUILT- IN STOP LAYER' [patent_app_type] => new [patent_app_number] => 09/140276 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2938 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046743.pdf [firstpage_image] =>[orig_patent_app_number] => 09140276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140276
Method for forming dual-polysilicon structures using a built-in stop layer Aug 25, 1998 Issued
Array ( [id] => 4357352 [patent_doc_number] => 06174794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of making high performance MOSFET with polished gate and source/drain feature' [patent_app_type] => 1 [patent_app_number] => 9/137275 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6102 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174794.pdf [firstpage_image] =>[orig_patent_app_number] => 137275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137275
Method of making high performance MOSFET with polished gate and source/drain feature Aug 19, 1998 Issued
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