Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4031442 [patent_doc_number] => 05907782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method of forming a multiple fin-pillar capacitor for a high density dram cell' [patent_app_type] => 1 [patent_app_number] => 9/134885 [patent_app_country] => US [patent_app_date] => 1998-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2964 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907782.pdf [firstpage_image] =>[orig_patent_app_number] => 134885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134885
Method of forming a multiple fin-pillar capacitor for a high density dram cell Aug 14, 1998 Issued
Array ( [id] => 4086950 [patent_doc_number] => 06133097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method for forming mirror image split gate flash memory devices by forming a central source line slot' [patent_app_type] => 1 [patent_app_number] => 9/133969 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 6958 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133097.pdf [firstpage_image] =>[orig_patent_app_number] => 133969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/133969
Method for forming mirror image split gate flash memory devices by forming a central source line slot Aug 13, 1998 Issued
Array ( [id] => 4191344 [patent_doc_number] => 06130134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Method for forming asymmetric flash EEPROM with a pocket to focus electron injections' [patent_app_type] => 1 [patent_app_number] => 9/134205 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4366 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130134.pdf [firstpage_image] =>[orig_patent_app_number] => 134205 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134205
Method for forming asymmetric flash EEPROM with a pocket to focus electron injections Aug 13, 1998 Issued
Array ( [id] => 4063754 [patent_doc_number] => 06008081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of forming electrostatic discharge protection structure of dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/126285 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3088 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 487 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008081.pdf [firstpage_image] =>[orig_patent_app_number] => 126285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/126285
Method of forming electrostatic discharge protection structure of dynamic random access memory Jul 29, 1998 Issued
Array ( [id] => 4125195 [patent_doc_number] => 06127248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Fabrication method for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/114154 [patent_app_country] => US [patent_app_date] => 1998-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1552 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127248.pdf [firstpage_image] =>[orig_patent_app_number] => 114154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114154
Fabrication method for semiconductor device Jul 12, 1998 Issued
09/114005 METHOD OF FABRICATING A BURIED BIT LINE Jul 9, 1998 Issued
Array ( [id] => 4063852 [patent_doc_number] => 06008088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method for fabricating a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/099615 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 38 [patent_no_of_words] => 4334 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008088.pdf [firstpage_image] =>[orig_patent_app_number] => 099615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099615
Method for fabricating a semiconductor memory device Jun 17, 1998 Issued
Array ( [id] => 4106624 [patent_doc_number] => 06022779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method of forming mask ROM' [patent_app_type] => 1 [patent_app_number] => 9/083106 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3337 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022779.pdf [firstpage_image] =>[orig_patent_app_number] => 083106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083106
Method of forming mask ROM May 21, 1998 Issued
Array ( [id] => 3950480 [patent_doc_number] => 05899722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method of forming dual spacer for self aligned contact integration' [patent_app_type] => 1 [patent_app_number] => 9/083417 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3140 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899722.pdf [firstpage_image] =>[orig_patent_app_number] => 083417 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083417
Method of forming dual spacer for self aligned contact integration May 21, 1998 Issued
Array ( [id] => 3945442 [patent_doc_number] => 05953616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method of fabricating a MOS device with a salicide structure' [patent_app_type] => 1 [patent_app_number] => 9/074595 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953616.pdf [firstpage_image] =>[orig_patent_app_number] => 074595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074595
Method of fabricating a MOS device with a salicide structure May 7, 1998 Issued
Array ( [id] => 4094800 [patent_doc_number] => 06096615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method of forming a semiconductor device having narrow gate electrode' [patent_app_type] => 1 [patent_app_number] => 9/069505 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2915 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096615.pdf [firstpage_image] =>[orig_patent_app_number] => 069505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069505
Method of forming a semiconductor device having narrow gate electrode Apr 28, 1998 Issued
Array ( [id] => 4070582 [patent_doc_number] => 05970352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Field effect transistor having elevated source and drain regions and methods for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/064716 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4007 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970352.pdf [firstpage_image] =>[orig_patent_app_number] => 064716 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064716
Field effect transistor having elevated source and drain regions and methods for manufacturing the same Apr 22, 1998 Issued
Array ( [id] => 3941492 [patent_doc_number] => 05989955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of forming stacked and trench type DRAM capacitor' [patent_app_type] => 1 [patent_app_number] => 9/063486 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3371 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989955.pdf [firstpage_image] =>[orig_patent_app_number] => 063486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063486
Method of forming stacked and trench type DRAM capacitor Apr 20, 1998 Issued
Array ( [id] => 4139349 [patent_doc_number] => 06060367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of forming capacitors' [patent_app_type] => 1 [patent_app_number] => 9/059686 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3137 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060367.pdf [firstpage_image] =>[orig_patent_app_number] => 059686 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059686
Method of forming capacitors Apr 13, 1998 Issued
09/058794 ROBUST METHOD OF FORMING A CYLINDER CAPACITOR FOR DRAM CIRCUITS Apr 12, 1998 Issued
Array ( [id] => 4084479 [patent_doc_number] => 06025223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Methods of forming high dielectric capacitors' [patent_app_type] => 1 [patent_app_number] => 9/057096 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3347 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025223.pdf [firstpage_image] =>[orig_patent_app_number] => 057096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057096
Methods of forming high dielectric capacitors Apr 7, 1998 Issued
Array ( [id] => 1354507 [patent_doc_number] => 06576521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method of forming semiconductor device with LDD structure' [patent_app_type] => B1 [patent_app_number] => 09/056555 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2558 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576521.pdf [firstpage_image] =>[orig_patent_app_number] => 09056555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056555
Method of forming semiconductor device with LDD structure Apr 6, 1998 Issued
Array ( [id] => 3944151 [patent_doc_number] => 05998260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for manufacturing DRAM capacitor' [patent_app_type] => 1 [patent_app_number] => 9/055685 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2944 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998260.pdf [firstpage_image] =>[orig_patent_app_number] => 055685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055685
Method for manufacturing DRAM capacitor Apr 5, 1998 Issued
Array ( [id] => 4145499 [patent_doc_number] => 06063660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Fabricating method of stacked type capacitor' [patent_app_type] => 1 [patent_app_number] => 9/052685 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 2322 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063660.pdf [firstpage_image] =>[orig_patent_app_number] => 052685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052685
Fabricating method of stacked type capacitor Mar 30, 1998 Issued
Array ( [id] => 4408413 [patent_doc_number] => 06300207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Depleted sidewall-poly LDD transistor' [patent_app_type] => 1 [patent_app_number] => 9/583105 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4911 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300207.pdf [firstpage_image] =>[orig_patent_app_number] => 583105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583105
Depleted sidewall-poly LDD transistor Mar 25, 1998 Issued
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