Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1241142 [patent_doc_number] => 06682965 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect' [patent_app_type] => B1 [patent_app_number] => 09/048288 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 10465 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/682/06682965.pdf [firstpage_image] =>[orig_patent_app_number] => 09048288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048288
Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect Mar 25, 1998 Issued
Array ( [id] => 3950466 [patent_doc_number] => 05899721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method of based spacer formation for ultra-small sapcer geometries' [patent_app_type] => 1 [patent_app_number] => 9/036744 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3991 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899721.pdf [firstpage_image] =>[orig_patent_app_number] => 036744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/036744
Method of based spacer formation for ultra-small sapcer geometries Mar 8, 1998 Issued
Array ( [id] => 3941478 [patent_doc_number] => 05989954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method for forming a cylinder capacitor in the dram process' [patent_app_type] => 1 [patent_app_number] => 9/035056 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2119 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989954.pdf [firstpage_image] =>[orig_patent_app_number] => 035056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035056
Method for forming a cylinder capacitor in the dram process Mar 4, 1998 Issued
Array ( [id] => 4141639 [patent_doc_number] => 06030868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation' [patent_app_type] => 1 [patent_app_number] => 9/033916 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6350 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030868.pdf [firstpage_image] =>[orig_patent_app_number] => 033916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033916
Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation Mar 2, 1998 Issued
Array ( [id] => 4063891 [patent_doc_number] => 06008089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of fabricating a split gate flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/033376 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2251 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008089.pdf [firstpage_image] =>[orig_patent_app_number] => 033376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033376
Method of fabricating a split gate flash memory device Mar 1, 1998 Issued
Array ( [id] => 4326645 [patent_doc_number] => 06319774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method for forming a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/044215 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4487 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319774.pdf [firstpage_image] =>[orig_patent_app_number] => 044215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044215
Method for forming a memory cell Feb 26, 1998 Issued
Array ( [id] => 4407131 [patent_doc_number] => 06238976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for forming high density flash memory' [patent_app_type] => 1 [patent_app_number] => 9/035304 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8194 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238976.pdf [firstpage_image] =>[orig_patent_app_number] => 035304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035304
Method for forming high density flash memory Feb 26, 1998 Issued
Array ( [id] => 4050793 [patent_doc_number] => 05943595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for manufacturing a semiconductor device having a triple-well structure' [patent_app_type] => 1 [patent_app_number] => 9/028570 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4368 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943595.pdf [firstpage_image] =>[orig_patent_app_number] => 028570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/028570
Method for manufacturing a semiconductor device having a triple-well structure Feb 23, 1998 Issued
09/027755 METHOD FOR INCREASING DRAM CAPACITANCE VIA USE OF A ROUGHENED SURFACE BOTTOM CAPACITOR PLATE Feb 22, 1998 Issued
Array ( [id] => 4357037 [patent_doc_number] => 06174774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/026690 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 3103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174774.pdf [firstpage_image] =>[orig_patent_app_number] => 026690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026690
Method of fabricating semiconductor device Feb 19, 1998 Issued
Array ( [id] => 3910701 [patent_doc_number] => 06001690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology' [patent_app_type] => 1 [patent_app_number] => 9/023066 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2888 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001690.pdf [firstpage_image] =>[orig_patent_app_number] => 023066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023066
Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology Feb 12, 1998 Issued
Array ( [id] => 4377593 [patent_doc_number] => 06303438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method for manufacturing a nonvolatile semiconductor memory device having increased hot electron injection efficiency' [patent_app_type] => 1 [patent_app_number] => 9/017216 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 33 [patent_no_of_words] => 9102 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303438.pdf [firstpage_image] =>[orig_patent_app_number] => 017216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/017216
Method for manufacturing a nonvolatile semiconductor memory device having increased hot electron injection efficiency Feb 1, 1998 Issued
Array ( [id] => 4408618 [patent_doc_number] => 06228709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of fabricating hemispherical grain electrode' [patent_app_type] => 1 [patent_app_number] => 9/010684 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1329 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228709.pdf [firstpage_image] =>[orig_patent_app_number] => 010684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010684
Method of fabricating hemispherical grain electrode Jan 21, 1998 Issued
Array ( [id] => 4069643 [patent_doc_number] => 05933722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method for manufacturing well structure in integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/009735 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2353 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933722.pdf [firstpage_image] =>[orig_patent_app_number] => 009735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009735
Method for manufacturing well structure in integrated circuit Jan 20, 1998 Issued
09/009300 METHOD OF FABRICATING TETRA-STATE MASK READ ONLY MEMORY Jan 19, 1998 Issued
Array ( [id] => 4101370 [patent_doc_number] => 06100123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Pillar CMOS structure' [patent_app_type] => 1 [patent_app_number] => 9/009456 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 3783 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100123.pdf [firstpage_image] =>[orig_patent_app_number] => 009456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009456
Pillar CMOS structure Jan 19, 1998 Issued
Array ( [id] => 4152378 [patent_doc_number] => 06124191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Self-aligned contact process using low density/low k dielectric' [patent_app_type] => 1 [patent_app_number] => 9/002196 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2357 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124191.pdf [firstpage_image] =>[orig_patent_app_number] => 002196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002196
Self-aligned contact process using low density/low k dielectric Dec 30, 1997 Issued
08/995534 METHOD OF FORMING A SEMICONDUCTOR DEVICE Dec 21, 1997 Abandoned
Array ( [id] => 1474485 [patent_doc_number] => 06387755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting' [patent_app_type] => B1 [patent_app_number] => 08/992616 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3085 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387755.pdf [firstpage_image] =>[orig_patent_app_number] => 08992616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992616
Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting Dec 16, 1997 Issued
Array ( [id] => 4046575 [patent_doc_number] => 05869379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method of forming air gap spacer for high performance MOSFETS\'' [patent_app_type] => 1 [patent_app_number] => 8/987116 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3669 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869379.pdf [firstpage_image] =>[orig_patent_app_number] => 987116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987116
Method of forming air gap spacer for high performance MOSFETS' Dec 7, 1997 Issued
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