Search

Darlington Ly

Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2962, 2914, 2917
Total Applications
4527
Issued Applications
4184
Pending Applications
73
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3910671 [patent_doc_number] => 06001688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method of eliminating poly stringer in a memory device' [patent_app_type] => 1 [patent_app_number] => 8/986860 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 4896 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001688.pdf [firstpage_image] =>[orig_patent_app_number] => 986860 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986860
Method of eliminating poly stringer in a memory device Dec 7, 1997 Issued
Array ( [id] => 4155216 [patent_doc_number] => 06114210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime' [patent_app_type] => 1 [patent_app_number] => 8/979364 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3706 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114210.pdf [firstpage_image] =>[orig_patent_app_number] => 979364 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979364
Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime Nov 25, 1997 Issued
Array ( [id] => 3759835 [patent_doc_number] => 05851866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Fabrication method for CMOS with sidewalls' [patent_app_type] => 1 [patent_app_number] => 8/979565 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3933 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851866.pdf [firstpage_image] =>[orig_patent_app_number] => 979565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979565
Fabrication method for CMOS with sidewalls Nov 25, 1997 Issued
Array ( [id] => 3806212 [patent_doc_number] => 05854115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length' [patent_app_type] => 1 [patent_app_number] => 8/979042 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3787 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854115.pdf [firstpage_image] =>[orig_patent_app_number] => 979042 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979042
Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length Nov 25, 1997 Issued
Array ( [id] => 3942176 [patent_doc_number] => 05946571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method of forming a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/975495 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4620 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946571.pdf [firstpage_image] =>[orig_patent_app_number] => 975495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975495
Method of forming a capacitor Nov 20, 1997 Issued
Array ( [id] => 3867552 [patent_doc_number] => 05837583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method of forming separated floating gate for EEPROM application' [patent_app_type] => 1 [patent_app_number] => 8/972634 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2815 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837583.pdf [firstpage_image] =>[orig_patent_app_number] => 972634 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972634
Method of forming separated floating gate for EEPROM application Nov 17, 1997 Issued
Array ( [id] => 3926084 [patent_doc_number] => 05877062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Methods of forming integrated circuit capacitors having protected diffusion barrier metal layers therein' [patent_app_type] => 1 [patent_app_number] => 8/969395 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877062.pdf [firstpage_image] =>[orig_patent_app_number] => 969395 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969395
Methods of forming integrated circuit capacitors having protected diffusion barrier metal layers therein Nov 12, 1997 Issued
Array ( [id] => 4097815 [patent_doc_number] => 06048767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method of forming a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/964416 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 6273 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048767.pdf [firstpage_image] =>[orig_patent_app_number] => 964416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964416
Method of forming a semiconductor memory device Nov 3, 1997 Issued
Array ( [id] => 4006766 [patent_doc_number] => 05888870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate' [patent_app_type] => 1 [patent_app_number] => 8/955794 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4171 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/888/05888870.pdf [firstpage_image] =>[orig_patent_app_number] => 955794 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955794
Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate Oct 21, 1997 Issued
Array ( [id] => 4009326 [patent_doc_number] => 05920781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method of making semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/951572 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 2926 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920781.pdf [firstpage_image] =>[orig_patent_app_number] => 951572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/951572
Method of making semiconductor device Oct 15, 1997 Issued
Array ( [id] => 4152098 [patent_doc_number] => 06124173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method for improved storage node isolation' [patent_app_type] => 1 [patent_app_number] => 8/940309 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3174 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124173.pdf [firstpage_image] =>[orig_patent_app_number] => 940309 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940309
Method for improved storage node isolation Sep 29, 1997 Issued
Array ( [id] => 6973604 [patent_doc_number] => 20010003666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'LIGHTLY DOPED DRAIN EXTENSION PROCESS TO MINIMIZE SOURCE/DRAIN RESISTANCE WHILE MAINTAINING HOT CARRIER LIFETIME' [patent_app_type] => new-utility [patent_app_number] => 08/934158 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003666.pdf [firstpage_image] =>[orig_patent_app_number] => 08934158 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934158
LIGHTLY DOPED DRAIN EXTENSION PROCESS TO MINIMIZE SOURCE/DRAIN RESISTANCE WHILE MAINTAINING HOT CARRIER LIFETIME Sep 18, 1997 Abandoned
Array ( [id] => 3965058 [patent_doc_number] => 05885886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/932830 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2182 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/885/05885886.pdf [firstpage_image] =>[orig_patent_app_number] => 932830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932830
Method for manufacturing semiconductor device Sep 17, 1997 Issued
Array ( [id] => 4002779 [patent_doc_number] => 06004848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method of forming a multi-level memory array with channel bias algorithm' [patent_app_type] => 1 [patent_app_number] => 8/927365 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5441 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004848.pdf [firstpage_image] =>[orig_patent_app_number] => 927365 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927365
Method of forming a multi-level memory array with channel bias algorithm Sep 8, 1997 Issued
Array ( [id] => 4381099 [patent_doc_number] => 06261902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of forming a transistor structure' [patent_app_type] => 1 [patent_app_number] => 8/925490 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2133 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261902.pdf [firstpage_image] =>[orig_patent_app_number] => 925490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925490
Method of forming a transistor structure Sep 7, 1997 Issued
Array ( [id] => 3996706 [patent_doc_number] => 05911106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Semiconductor memory device and fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/920460 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3441 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911106.pdf [firstpage_image] =>[orig_patent_app_number] => 920460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920460
Semiconductor memory device and fabrication thereof Aug 28, 1997 Issued
Array ( [id] => 4064446 [patent_doc_number] => 06008129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Process for forming a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/919406 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2161 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008129.pdf [firstpage_image] =>[orig_patent_app_number] => 919406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919406
Process for forming a semiconductor device Aug 27, 1997 Issued
Array ( [id] => 4030963 [patent_doc_number] => 05963806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method of forming memory cell with built-in erasure feature' [patent_app_type] => 1 [patent_app_number] => 8/916758 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3865 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963806.pdf [firstpage_image] =>[orig_patent_app_number] => 916758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916758
Method of forming memory cell with built-in erasure feature Aug 18, 1997 Issued
Array ( [id] => 4018090 [patent_doc_number] => 05902133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method of forming a narrow polysilicon gate with i-line lithography' [patent_app_type] => 1 [patent_app_number] => 8/910268 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1990 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/902/05902133.pdf [firstpage_image] =>[orig_patent_app_number] => 910268 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910268
Method of forming a narrow polysilicon gate with i-line lithography Aug 12, 1997 Issued
Array ( [id] => 4130047 [patent_doc_number] => 06033954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method of fabricating flash memory cell' [patent_app_type] => 1 [patent_app_number] => 8/908922 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2093 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033954.pdf [firstpage_image] =>[orig_patent_app_number] => 908922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908922
Method of fabricating flash memory cell Aug 7, 1997 Issued
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