
Darlington Ly
Examiner (ID: 22, Phone: (571)272-2617 , Office: P/2914 )
| Most Active Art Unit | 2914 |
| Art Unit(s) | 2962, 2914, 2917 |
| Total Applications | 4527 |
| Issued Applications | 4184 |
| Pending Applications | 73 |
| Abandoned Applications | 287 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4245917
[patent_doc_number] => 06136658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Method of fabricating a semiconductor device including a contact hole between gate electrode structures'
[patent_app_type] => 1
[patent_app_number] => 8/891081
[patent_app_country] => US
[patent_app_date] => 1997-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 34
[patent_no_of_words] => 8071
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/136/06136658.pdf
[firstpage_image] =>[orig_patent_app_number] => 891081
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/891081 | Method of fabricating a semiconductor device including a contact hole between gate electrode structures | Jul 9, 1997 | Issued |
Array
(
[id] => 4215330
[patent_doc_number] => 06087228
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Method of making a nonvolatile memory cell using EPROM mask and ROM processing steps'
[patent_app_type] => 1
[patent_app_number] => 8/890052
[patent_app_country] => US
[patent_app_date] => 1997-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2123
[patent_no_of_claims] => 6
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[patent_words_short_claim] => 156
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/087/06087228.pdf
[firstpage_image] =>[orig_patent_app_number] => 890052
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/890052 | Method of making a nonvolatile memory cell using EPROM mask and ROM processing steps | Jul 8, 1997 | Issued |
Array
(
[id] => 4006795
[patent_doc_number] => 05888872
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall'
[patent_app_type] => 1
[patent_app_number] => 8/879574
[patent_app_country] => US
[patent_app_date] => 1997-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4032
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[pdf_file] => patents/05/888/05888872.pdf
[firstpage_image] =>[orig_patent_app_number] => 879574
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879574 | Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall | Jun 19, 1997 | Issued |
Array
(
[id] => 4328540
[patent_doc_number] => 06312965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Method for sharpening emitter sites using low temperature oxidation process'
[patent_app_type] => 1
[patent_app_number] => 8/878276
[patent_app_country] => US
[patent_app_date] => 1997-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4421
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/312/06312965.pdf
[firstpage_image] =>[orig_patent_app_number] => 878276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/878276 | Method for sharpening emitter sites using low temperature oxidation process | Jun 17, 1997 | Issued |
Array
(
[id] => 3873121
[patent_doc_number] => 05824584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Method of making and accessing split gate memory device'
[patent_app_type] => 1
[patent_app_number] => 8/876326
[patent_app_country] => US
[patent_app_date] => 1997-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 4653
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/824/05824584.pdf
[firstpage_image] =>[orig_patent_app_number] => 876326
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/876326 | Method of making and accessing split gate memory device | Jun 15, 1997 | Issued |
Array
(
[id] => 3938325
[patent_doc_number] => 05872047
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Method for forming shallow junction of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/871850
[patent_app_country] => US
[patent_app_date] => 1997-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2303
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[pdf_file] => patents/05/872/05872047.pdf
[firstpage_image] =>[orig_patent_app_number] => 871850
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/871850 | Method for forming shallow junction of a semiconductor device | Jun 8, 1997 | Issued |
Array
(
[id] => 4357774
[patent_doc_number] => 06174821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'Semiconductor processing method of depositing polysilicon'
[patent_app_type] => 1
[patent_app_number] => 8/868057
[patent_app_country] => US
[patent_app_date] => 1997-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1898
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/174/06174821.pdf
[firstpage_image] =>[orig_patent_app_number] => 868057
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/868057 | Semiconductor processing method of depositing polysilicon | Jun 2, 1997 | Issued |
Array
(
[id] => 4029343
[patent_doc_number] => 05994179
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Method of fabricating a MOSFET featuring an effective suppression of reverse short-channel effect'
[patent_app_type] => 1
[patent_app_number] => 8/867020
[patent_app_country] => US
[patent_app_date] => 1997-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 28
[patent_no_of_words] => 3723
[patent_no_of_claims] => 26
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994179.pdf
[firstpage_image] =>[orig_patent_app_number] => 867020
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867020 | Method of fabricating a MOSFET featuring an effective suppression of reverse short-channel effect | Jun 2, 1997 | Issued |
Array
(
[id] => 4106665
[patent_doc_number] => 06022782
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Method for forming integrated circuit transistors using sacrificial spacer'
[patent_app_type] => 1
[patent_app_number] => 8/866895
[patent_app_country] => US
[patent_app_date] => 1997-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2320
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[pdf_file] => patents/06/022/06022782.pdf
[firstpage_image] =>[orig_patent_app_number] => 866895
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/866895 | Method for forming integrated circuit transistors using sacrificial spacer | May 29, 1997 | Issued |
Array
(
[id] => 4003755
[patent_doc_number] => 05960252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Method for manufacturing a semiconductor memory device having a ferroelectric capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/846546
[patent_app_country] => US
[patent_app_date] => 1997-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/960/05960252.pdf
[firstpage_image] =>[orig_patent_app_number] => 846546
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/846546 | Method for manufacturing a semiconductor memory device having a ferroelectric capacitor | Apr 29, 1997 | Issued |
Array
(
[id] => 4206748
[patent_doc_number] => 06027980
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Method of forming a decoupling capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/848506
[patent_app_country] => US
[patent_app_date] => 1997-04-28
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[pdf_file] => patents/06/027/06027980.pdf
[firstpage_image] =>[orig_patent_app_number] => 848506
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/848506 | Method of forming a decoupling capacitor | Apr 27, 1997 | Issued |
Array
(
[id] => 4293662
[patent_doc_number] => 06197645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls'
[patent_app_type] => 1
[patent_app_number] => 8/837539
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 837539
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837539 | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls | Apr 20, 1997 | Issued |
Array
(
[id] => 4016431
[patent_doc_number] => 05923982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps'
[patent_app_type] => 1
[patent_app_number] => 8/837526
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837526 | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps | Apr 20, 1997 | Issued |
Array
(
[id] => 3926056
[patent_doc_number] => 05877060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Method for fabricating SRAM polyload'
[patent_app_type] => 1
[patent_app_number] => 8/837462
[patent_app_country] => US
[patent_app_date] => 1997-04-18
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[firstpage_image] =>[orig_patent_app_number] => 837462
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837462 | Method for fabricating SRAM polyload | Apr 17, 1997 | Issued |
Array
(
[id] => 3938135
[patent_doc_number] => 05872035
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Method of forming a floating gate in a flash memory device'
[patent_app_type] => 1
[patent_app_number] => 8/834398
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[firstpage_image] =>[orig_patent_app_number] => 834398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/834398 | Method of forming a floating gate in a flash memory device | Apr 15, 1997 | Issued |
Array
(
[id] => 4124720
[patent_doc_number] => 06127218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Methods for forming ferroelectric films using dual deposition steps'
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[patent_app_number] => 8/843506
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[firstpage_image] =>[orig_patent_app_number] => 843506
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/843506 | Methods for forming ferroelectric films using dual deposition steps | Apr 15, 1997 | Issued |
Array
(
[id] => 4408581
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[patent_country] => US
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[patent_issue_date] => 2001-10-09
[patent_title] => 'Method of forming die seal structures having substrate trenches'
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[firstpage_image] =>[orig_patent_app_number] => 828422
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/828422 | Method of forming die seal structures having substrate trenches | Mar 27, 1997 | Issued |
Array
(
[id] => 3877273
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/814138 | Increased capacitor surface area via use of an oxide formation and removal procedure | Mar 9, 1997 | Issued |
Array
(
[id] => 6986920
[patent_doc_number] => 20010036752
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[patent_issue_date] => 2001-11-01
[patent_title] => 'METHODS AND APPARATUS FOR FORMING A HIGH DIELECTRIC FILM AND THE DIELECTRIC FILM FORMED THEREBY'
[patent_app_type] => new
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[pdf_file] => publications/A1/0036/20010036752.pdf
[firstpage_image] =>[orig_patent_app_number] => 08807831
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/807831 | Methods for forming a dielectric film | Feb 26, 1997 | Issued |
Array
(
[id] => 3886030
[patent_doc_number] => 05893740
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[patent_kind] => NA
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[patent_title] => 'Method of forming a short channel field effect transistor'
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[patent_app_country] => US
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[pdf_file] => patents/05/893/05893740.pdf
[firstpage_image] =>[orig_patent_app_number] => 788254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/788254 | Method of forming a short channel field effect transistor | Jan 26, 1997 | Issued |