Search

Darrell G Dayoan

Examiner (ID: 10437)

Most Active Art Unit
3101
Art Unit(s)
3107, 3101, 3612, 3615, 2899
Total Applications
1472
Issued Applications
1258
Pending Applications
45
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14969327 [patent_doc_number] => 20190312142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => SEALED CAVITY STRUCTURES WITH NON-PLANAR SURFACE FEATURES TO INDUCE STRESS [patent_app_type] => utility [patent_app_number] => 15/947364 [patent_app_country] => US [patent_app_date] => 2018-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/947364
Sealed cavity structures with non-planar surface features to induce stress Apr 5, 2018 Issued
Array ( [id] => 14968961 [patent_doc_number] => 20190311959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => HIGH DENSITY WAFER LEVEL TEST MODULE [patent_app_type] => utility [patent_app_number] => 15/946386 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946386
High density wafer level test module Apr 4, 2018 Issued
Array ( [id] => 14969017 [patent_doc_number] => 20190311987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => Through-Core Via [patent_app_type] => utility [patent_app_number] => 15/946139 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -47 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946139
Through-core via Apr 4, 2018 Issued
Array ( [id] => 14969033 [patent_doc_number] => 20190311995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => WARPING REDUCTION IN SILICON WAFERS [patent_app_type] => utility [patent_app_number] => 15/945665 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945665 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/945665
Warping reduction in silicon wafers Apr 3, 2018 Issued
Array ( [id] => 13349427 [patent_doc_number] => 20180226253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/943261 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943261
Method for manufacturing substrate for semiconductor device Apr 1, 2018 Issued
Array ( [id] => 15015377 [patent_doc_number] => 10453849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Dynamic random access memory structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/936396 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3812 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/936396
Dynamic random access memory structure and method for forming the same Mar 25, 2018 Issued
Array ( [id] => 14492365 [patent_doc_number] => 10332983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Vertical field-effect transistors including uniform gate lengths [patent_app_type] => utility [patent_app_number] => 15/935468 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 9023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935468 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/935468
Vertical field-effect transistors including uniform gate lengths Mar 25, 2018 Issued
Array ( [id] => 14671907 [patent_doc_number] => 10373873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Gate cut in replacement metal gate process [patent_app_type] => utility [patent_app_number] => 15/933708 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 36 [patent_no_of_words] => 7065 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933708 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933708
Gate cut in replacement metal gate process Mar 22, 2018 Issued
Array ( [id] => 13451819 [patent_doc_number] => 20180277452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => INSPECTION OF SUBSTRATES [patent_app_type] => utility [patent_app_number] => 15/933366 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933366 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933366
Inspection of substrates Mar 21, 2018 Issued
Array ( [id] => 16035019 [patent_doc_number] => 10679942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Electrical junction for facilitating an integration of electrical crossing [patent_app_type] => utility [patent_app_number] => 15/922167 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4404 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922167 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922167
Electrical junction for facilitating an integration of electrical crossing Mar 14, 2018 Issued
Array ( [id] => 14603473 [patent_doc_number] => 10354932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Semiconductor device including semiconductor element and redistribution layer electrically connected thereto, and method of manufacturing the device [patent_app_type] => utility [patent_app_number] => 15/920863 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 19860 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920863
Semiconductor device including semiconductor element and redistribution layer electrically connected thereto, and method of manufacturing the device Mar 13, 2018 Issued
Array ( [id] => 12918226 [patent_doc_number] => 20180197918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => Resistive Change Elements Incorporating Carbon Based Diode Select Devices [patent_app_type] => utility [patent_app_number] => 15/911246 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 63591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -43 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911246 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911246
Resistive change elements incorporating carbon based diode select devices Mar 4, 2018 Issued
Array ( [id] => 14267713 [patent_doc_number] => 10283427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Molding structure for wafer level package [patent_app_type] => utility [patent_app_number] => 15/911281 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911281
Molding structure for wafer level package Mar 4, 2018 Issued
Array ( [id] => 12896272 [patent_doc_number] => 20180190599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => Multi-Die Integrated Circuit Device With Capacitive Overvoltage Protection [patent_app_type] => utility [patent_app_number] => 15/907445 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907445
Multi-die integrated circuit device with capacitive overvoltage protection Feb 27, 2018 Issued
Array ( [id] => 14707257 [patent_doc_number] => 10381389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Solid state imaging device, manufacturing method of solid state imaging device, and imaging system [patent_app_type] => utility [patent_app_number] => 15/897940 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 12975 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897940
Solid state imaging device, manufacturing method of solid state imaging device, and imaging system Feb 14, 2018 Issued
Array ( [id] => 14205477 [patent_doc_number] => 10269864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Pixel isolation device and fabrication method [patent_app_type] => utility [patent_app_number] => 15/888907 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888907
Pixel isolation device and fabrication method Feb 4, 2018 Issued
Array ( [id] => 14333415 [patent_doc_number] => 10297737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Method of manufacturing light emitting device with exposed wire end portions [patent_app_type] => utility [patent_app_number] => 15/886656 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 41 [patent_no_of_words] => 18330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886656 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886656
Method of manufacturing light emitting device with exposed wire end portions Jan 31, 2018 Issued
Array ( [id] => 16034247 [patent_doc_number] => 10679550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 15/885894 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 87 [patent_no_of_words] => 27062 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885894 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885894
Display device Jan 31, 2018 Issued
Array ( [id] => 15250281 [patent_doc_number] => 10510669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Multi-chip package and method of providing die-to-die interconnects in same [patent_app_type] => utility [patent_app_number] => 15/876080 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 10144 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876080 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876080
Multi-chip package and method of providing die-to-die interconnects in same Jan 18, 2018 Issued
Array ( [id] => 12801361 [patent_doc_number] => 20180158956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/872154 [patent_app_country] => US [patent_app_date] => 2018-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15872154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/872154
Semiconductor device having insulating film including low-density region Jan 15, 2018 Issued
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