Search

Darrell G Dayoan

Examiner (ID: 10437)

Most Active Art Unit
3101
Art Unit(s)
3107, 3101, 3612, 3615, 2899
Total Applications
1472
Issued Applications
1258
Pending Applications
45
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10610862 [patent_doc_number] => 09330902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-03 [patent_title] => 'Method for forming HfOx film based on atomic layer deposition (ALD) process' [patent_app_type] => utility [patent_app_number] => 14/731227 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3262 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731227 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731227
Method for forming HfOx film based on atomic layer deposition (ALD) process Jun 3, 2015 Issued
Array ( [id] => 11391767 [patent_doc_number] => 09553017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures' [patent_app_type] => utility [patent_app_number] => 14/729342 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3855 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729342
Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures Jun 2, 2015 Issued
Array ( [id] => 11259369 [patent_doc_number] => 09484274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Methods for reducing semiconductor substrate strain variation' [patent_app_type] => utility [patent_app_number] => 14/730198 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730198
Methods for reducing semiconductor substrate strain variation Jun 2, 2015 Issued
Array ( [id] => 10472508 [patent_doc_number] => 20150357526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'ELECTROPHOTOGRAPHIC DEPOSITION OF UNPACKAGED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/729745 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729745
Electrophotographic deposition of unpackaged semiconductor device Jun 2, 2015 Issued
Array ( [id] => 11050728 [patent_doc_number] => 20160247687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'PATTERN FORMING METHOD AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/729474 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729474 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729474
Pattern forming method and manufacturing method for semiconductor device Jun 2, 2015 Issued
Array ( [id] => 13201797 [patent_doc_number] => 10115819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Recessed high voltage metal oxide semiconductor transistor for RRAM cell [patent_app_type] => utility [patent_app_number] => 14/726071 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 11175 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726071
Recessed high voltage metal oxide semiconductor transistor for RRAM cell May 28, 2015 Issued
Array ( [id] => 10453706 [patent_doc_number] => 20150338720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'PHOTONIC CMOS INVERTER' [patent_app_type] => utility [patent_app_number] => 14/719580 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14719580 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/719580
CMOS photonic inverter May 21, 2015 Issued
Array ( [id] => 10370501 [patent_doc_number] => 20150255506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/717288 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4984 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14717288 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/717288
Semiconductor storage device May 19, 2015 Issued
Array ( [id] => 10351095 [patent_doc_number] => 20150236100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 14/702608 [patent_app_country] => US [patent_app_date] => 2015-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5721 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702608 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/702608
Field effect transistor with narrow bandgap source and drain regions and method of fabrication Apr 30, 2015 Issued
Array ( [id] => 11130863 [patent_doc_number] => 20160327838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/905738 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14905738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/905738
Array substrate, display panel and display device Apr 19, 2015 Issued
Array ( [id] => 10336861 [patent_doc_number] => 20150221866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'HORIZONTALLY ORIENTED AND VERTICALLY STACKED MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 14/688502 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7250 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688502
Horizontally oriented and vertically stacked memory cells Apr 15, 2015 Issued
Array ( [id] => 10329298 [patent_doc_number] => 20150214302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/683670 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5979 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683670 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683670
Three-dimensional quantum well transistor Apr 9, 2015 Issued
Array ( [id] => 10329416 [patent_doc_number] => 20150214420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'MICRO DEVICE WITH STABILIZATION POST' [patent_app_type] => utility [patent_app_number] => 14/681715 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9417 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681715 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/681715
Micro device with stabilization post Apr 7, 2015 Issued
Array ( [id] => 11096633 [patent_doc_number] => 20160293602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'VERTICAL JUNCTION FINFET DEVICE AND METHOD FOR MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/677404 [patent_app_country] => US [patent_app_date] => 2015-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2756 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14677404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/677404
Vertical junction FinFET device and method for manufacture Apr 1, 2015 Issued
Array ( [id] => 11043696 [patent_doc_number] => 20160240652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'FINFETS with Wrap-Around Silicide and Method Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/675215 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9124 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675215
FINFETs with wrap-around silicide and method forming the same Mar 30, 2015 Issued
Array ( [id] => 11096652 [patent_doc_number] => 20160293621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'BRIDGE LINE STRUCTURE FOR BIT LINE CONNECTION IN A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/675162 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 75 [patent_no_of_words] => 22908 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675162 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675162
Bridge line structure for bit line connection in a three-dimensional semiconductor device Mar 30, 2015 Issued
Array ( [id] => 11221703 [patent_doc_number] => 09450047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-20 [patent_title] => 'Semiconductor structure having enlarged regrowth regions and manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 14/674474 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14674474 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/674474
Semiconductor structure having enlarged regrowth regions and manufacturing method of the same Mar 30, 2015 Issued
Array ( [id] => 11096481 [patent_doc_number] => 20160293450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR DEVICE WITH SLOPED SIDEWALL AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/672664 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2164 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672664
Semiconductor device with sloped sidewall and related methods Mar 29, 2015 Issued
Array ( [id] => 10583650 [patent_doc_number] => 09305775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Fabrication method of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/668330 [patent_app_country] => US [patent_app_date] => 2015-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4846 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14668330 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/668330
Fabrication method of semiconductor memory device Mar 24, 2015 Issued
Array ( [id] => 10519041 [patent_doc_number] => 09246097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Diffusion barrier layer for resistive random access memory cells' [patent_app_type] => utility [patent_app_number] => 14/644382 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9179 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14644382 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/644382
Diffusion barrier layer for resistive random access memory cells Mar 10, 2015 Issued
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