Search

Darrell G Dayoan

Examiner (ID: 10437)

Most Active Art Unit
3101
Art Unit(s)
3107, 3101, 3612, 3615, 2899
Total Applications
1472
Issued Applications
1258
Pending Applications
45
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10645287 [patent_doc_number] => 09362162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Methods of fabricating BEOL interlayer structures' [patent_app_type] => utility [patent_app_number] => 14/459444 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459444
Methods of fabricating BEOL interlayer structures Aug 13, 2014 Issued
Array ( [id] => 11259377 [patent_doc_number] => 09484281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Systems and methods for thermal dissipation' [patent_app_type] => utility [patent_app_number] => 14/459319 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459319 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459319
Systems and methods for thermal dissipation Aug 13, 2014 Issued
Array ( [id] => 10165347 [patent_doc_number] => 09196578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-24 [patent_title] => 'Common pin for multi-die semiconductor package' [patent_app_type] => utility [patent_app_number] => 14/459337 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2273 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459337
Common pin for multi-die semiconductor package Aug 13, 2014 Issued
Array ( [id] => 10178815 [patent_doc_number] => 09209027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-08 [patent_title] => 'Adjusting the charge carrier lifetime in a bipolar semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/459391 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 9684 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459391 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459391
Adjusting the charge carrier lifetime in a bipolar semiconductor device Aug 13, 2014 Issued
Array ( [id] => 10703232 [patent_doc_number] => 20160049380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'WIRE BONDS FOR ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 14/459011 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1648 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459011 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459011
Wire bonds for electronics Aug 12, 2014 Issued
Array ( [id] => 10703155 [patent_doc_number] => 20160049302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR CIRCUIT ELEMENT AND SEMICONDUCTOR CIRCUIT ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/458718 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458718 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458718
Methods of forming a semiconductor circuit element and semiconductor circuit element Aug 12, 2014 Issued
Array ( [id] => 11201276 [patent_doc_number] => 09431496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Dual work function buried gate-type transistor, method for forming the same, and electronic device including the same' [patent_app_type] => utility [patent_app_number] => 14/458986 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 9435 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458986
Dual work function buried gate-type transistor, method for forming the same, and electronic device including the same Aug 12, 2014 Issued
Array ( [id] => 10703269 [patent_doc_number] => 20160049416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS' [patent_app_type] => utility [patent_app_number] => 14/458542 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4537 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458542 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458542
Integration of semiconductor memory cells and logic cells Aug 12, 2014 Issued
Array ( [id] => 10703335 [patent_doc_number] => 20160049482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACK' [patent_app_type] => utility [patent_app_number] => 14/458588 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458588 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458588
Structure and formation method of semiconductor device with gate stack Aug 12, 2014 Issued
Array ( [id] => 10378150 [patent_doc_number] => 20150263156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/458645 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7926 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458645 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458645
Semiconductor transistor device Aug 12, 2014 Issued
Array ( [id] => 11103973 [patent_doc_number] => 20160300943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'SILICON CARBIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/026842 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8046 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15026842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/026842
Silicon carbide semiconductor device Aug 10, 2014 Issued
Array ( [id] => 10943417 [patent_doc_number] => 20140346438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/454581 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454581 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454581
Semiconductor light emitting device and method for manufacturing the same Aug 6, 2014 Issued
Array ( [id] => 11206418 [patent_doc_number] => 09436044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Array substrate, driving method of array substrate, and display device' [patent_app_type] => utility [patent_app_number] => 14/429105 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5438 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14429105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/429105
Array substrate, driving method of array substrate, and display device Jul 29, 2014 Issued
Array ( [id] => 10106713 [patent_doc_number] => 09142496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-22 [patent_title] => 'Semiconductor package having etched foil capacitor integrated into leadframe' [patent_app_type] => utility [patent_app_number] => 14/444370 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2709 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444370 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/444370
Semiconductor package having etched foil capacitor integrated into leadframe Jul 27, 2014 Issued
Array ( [id] => 10538029 [patent_doc_number] => 09263667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-16 [patent_title] => 'Method for manufacturing MTJ memory device' [patent_app_type] => utility [patent_app_number] => 14/341185 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14341185 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/341185
Method for manufacturing MTJ memory device Jul 24, 2014 Issued
Array ( [id] => 10929816 [patent_doc_number] => 20140332837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'LIGHT EMITTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/338812 [patent_app_country] => US [patent_app_date] => 2014-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3448 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14338812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/338812
Light emitting apparatus Jul 22, 2014 Issued
Array ( [id] => 11694440 [patent_doc_number] => 20170170157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'Power Transistor Module' [patent_app_type] => utility [patent_app_number] => 15/325784 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15325784 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/325784
Power transistor module Jul 14, 2014 Issued
Array ( [id] => 10916615 [patent_doc_number] => 20140319633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'MAGNETIC MEMORY ELEMENT AND MEMORY APPARATUS HAVING MULTIPLE MAGNETIZATION DIRECTIONS' [patent_app_type] => utility [patent_app_number] => 14/330748 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11216 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330748
Magnetic memory element and memory apparatus having multiple magnetization directions Jul 13, 2014 Issued
Array ( [id] => 12019708 [patent_doc_number] => 09812420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Die packaging with fully or partially fused dielectric leads' [patent_app_type] => utility [patent_app_number] => 14/902504 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5998 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902504
Die packaging with fully or partially fused dielectric leads Jul 1, 2014 Issued
Array ( [id] => 11753461 [patent_doc_number] => 09711479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Substrate less die package having wires with dielectric and metal coatings and the method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/902360 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2862 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902360 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902360
Substrate less die package having wires with dielectric and metal coatings and the method of manufacturing the same Jul 1, 2014 Issued
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