| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 6026807
[patent_doc_number] => 20110079794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-07
[patent_title] => 'METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/964579
[patent_app_country] => US
[patent_app_date] => 2010-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4143
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20110079794.pdf
[firstpage_image] =>[orig_patent_app_number] => 12964579
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/964579 | Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices | Dec 8, 2010 | Issued |
Array
(
[id] => 6118385
[patent_doc_number] => 20110076058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'SURFACE EMITTING LASER MANUFACTURING METHOD, SURFACE EMITTING LASER ARRAY MANUFACTURING METHOD, SURFACE EMITTING LASER, SURFACE EMITTING LASER ARRAY, AND OPTICAL APPARATUS INCLUDING SURFACE EMITTING LASER ARRAY'
[patent_app_type] => utility
[patent_app_number] => 12/958987
[patent_app_country] => US
[patent_app_date] => 2010-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11540
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20110076058.pdf
[firstpage_image] =>[orig_patent_app_number] => 12958987
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/958987 | Surface emitting laser manufacturing method, surface emitting laser array manufacturing method, surface emitting laser, surface emitting laser array, and optical apparatus including surface emitting laser array | Dec 1, 2010 | Issued |
Array
(
[id] => 7702886
[patent_doc_number] => 08088640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953721
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/088/08088640.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953721
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953721 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 7555362
[patent_doc_number] => 08067263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-29
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953716
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6538
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/067/08067263.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953716
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953716 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 7977349
[patent_doc_number] => 08071421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953701
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/071/08071421.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953701
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953701 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 8005783
[patent_doc_number] => 08084292
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953729
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/084/08084292.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953729
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953729 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 4608700
[patent_doc_number] => 07993955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953679
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/993/07993955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953679
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953679 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 4492617
[patent_doc_number] => 07955891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-07
[patent_title] => 'Thermal management and method for large scale processing of CIS and /or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953697
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/955/07955891.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953697
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953697 | Thermal management and method for large scale processing of CIS and /or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 4608699
[patent_doc_number] => 07993954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953674
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/993/07993954.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953674
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953674 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 5976934
[patent_doc_number] => 20110070686
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-24
[patent_title] => 'THERMAL MANAGEMENT AND METHOD FOR LARGE SCALE PROCESSING OF CIS AND/OR CIGS BASED THIN FILMS OVERLYING GLASS SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 12/953708
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20110070686.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953708
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953708 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 8005781
[patent_doc_number] => 08084291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953725
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6553
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/084/08084291.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953725
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953725 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 7777572
[patent_doc_number] => 20120040531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-16
[patent_title] => 'METHOD TO FABRICATE THIN METAL VIA INTERCONNECTS ON COPPER WIRES IN MRAM DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/806381
[patent_app_country] => US
[patent_app_date] => 2010-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8612
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20120040531.pdf
[firstpage_image] =>[orig_patent_app_number] => 12806381
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/806381 | Method to fabricate thin metal via interconnects on copper wires in MRAM devices | Aug 10, 2010 | Issued |
Array
(
[id] => 8017131
[patent_doc_number] => 08138068
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-20
[patent_title] => 'Method to form nanopore array'
[patent_app_type] => utility
[patent_app_number] => 12/854192
[patent_app_country] => US
[patent_app_date] => 2010-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 30
[patent_no_of_words] => 7823
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/138/08138068.pdf
[firstpage_image] =>[orig_patent_app_number] => 12854192
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/854192 | Method to form nanopore array | Aug 10, 2010 | Issued |
Array
(
[id] => 6130619
[patent_doc_number] => 20110006372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-13
[patent_title] => 'FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/834231
[patent_app_country] => US
[patent_app_date] => 2010-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5670
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20110006372.pdf
[firstpage_image] =>[orig_patent_app_number] => 12834231
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/834231 | Formation of standard voltage threshold and low voltage threshold MOSFET devices | Jul 11, 2010 | Issued |
Array
(
[id] => 8292283
[patent_doc_number] => RE043521
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2012-07-17
[patent_title] => 'Method for manufacturing semiconductor device, including multiple heat treatment'
[patent_app_type] => reissue
[patent_app_number] => 12/819339
[patent_app_country] => US
[patent_app_date] => 2010-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 8509
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12819339
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/819339 | Method for manufacturing semiconductor device, including multiple heat treatment | Jun 20, 2010 | Issued |
Array
(
[id] => 5985739
[patent_doc_number] => 20110097846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-28
[patent_title] => 'SEMICONDUCTOR CHIP, WAFER STACK PACKAGE USING THE SAME, AND METHODS OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/817304
[patent_app_country] => US
[patent_app_date] => 2010-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6470
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20110097846.pdf
[firstpage_image] =>[orig_patent_app_number] => 12817304
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/817304 | Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same | Jun 16, 2010 | Issued |
Array
(
[id] => 8005901
[patent_doc_number] => 08084351
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Contact structure of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/776923
[patent_app_country] => US
[patent_app_date] => 2010-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3016
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/084/08084351.pdf
[firstpage_image] =>[orig_patent_app_number] => 12776923
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/776923 | Contact structure of a semiconductor device | May 9, 2010 | Issued |
Array
(
[id] => 6570007
[patent_doc_number] => 20100273304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-28
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/760152
[patent_app_country] => US
[patent_app_date] => 2010-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3890
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20100273304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12760152
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/760152 | Method of fabricating semiconductor device | Apr 13, 2010 | Issued |
Array
(
[id] => 8317360
[patent_doc_number] => 08232138
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-31
[patent_title] => 'Circuit board with notched stiffener frame'
[patent_app_type] => utility
[patent_app_number] => 12/759761
[patent_app_country] => US
[patent_app_date] => 2010-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4486
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759761
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/759761 | Circuit board with notched stiffener frame | Apr 13, 2010 | Issued |
Array
(
[id] => 7486111
[patent_doc_number] => 20110250725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK'
[patent_app_type] => utility
[patent_app_number] => 12/758491
[patent_app_country] => US
[patent_app_date] => 2010-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4091
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20110250725.pdf
[firstpage_image] =>[orig_patent_app_number] => 12758491
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/758491 | Method of fabricating gate electrode using a treated hard mask | Apr 11, 2010 | Issued |